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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-17 18:21:24 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-17 18:21:24 +0000 |
| commit | f1fddcd9e01ceb38ee7f2951f9e109cccb601654 (patch) | |
| tree | af9c1d2d93aa4a56a520a27c9f09869445f77bbd /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 2d0a61da62b19d9597d569fb99082b418e214a12 (diff) | |
| download | llvm-f1fddcd9e01ceb38ee7f2951f9e109cccb601654.tar.gz llvm-f1fddcd9e01ceb38ee7f2951f9e109cccb601654.tar.bz2 llvm-f1fddcd9e01ceb38ee7f2951f9e109cccb601654.tar.xz | |
Redefine multiply and divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142211 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 29cc76ce44..f2eb700e5e 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -52,17 +52,10 @@ class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm, CPU64Regs>; // Mul, Div -let Defs = [HI64, LO64] in { - let isCommutable = 1 in - class Mul64<bits<6> func, string instr_asm, InstrItinClass itin>: - FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b), - !strconcat(instr_asm, "\t$a, $b"), [], itin>; - - class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: - FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b), - !strconcat(instr_asm, "\t$$zero, $a, $b"), - [(op CPU64Regs:$a, CPU64Regs:$b)], itin>; -} +class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: + Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; +class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: + Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; // Move from Hi/Lo let shamt = 0 in { @@ -159,8 +152,8 @@ def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>; def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; /// Multiply and Divide Instructions. -def DMULT : Mul64<0x1c, "dmult", IIImul>; -def DMULTu : Mul64<0x1d, "dmultu", IIImul>; +def DMULT : Mult64<0x1c, "dmult", IIImul>; +def DMULTu : Mult64<0x1d, "dmultu", IIImul>; def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; |