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authorMatheus Almeida <matheus.almeida@imgtec.com>2014-02-10 12:05:17 +0000
committerMatheus Almeida <matheus.almeida@imgtec.com>2014-02-10 12:05:17 +0000
commit3f14ca5e3027bae10203ea02e716a1a4c6fddf80 (patch)
tree8204d1d596830ae72feff848c04457955a25cb27 /lib/Target/Mips/MipsMSAInstrFormats.td
parent5f09dd31f0220d54c32464ce7ca19b1af17ec984 (diff)
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[mips][msa] Add DLSA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201081 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsMSAInstrFormats.td')
-rw-r--r--lib/Target/Mips/MipsMSAInstrFormats.td18
1 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td
index 3942d05914..6bd0366b52 100644
--- a/lib/Target/Mips/MipsMSAInstrFormats.td
+++ b/lib/Target/Mips/MipsMSAInstrFormats.td
@@ -27,6 +27,10 @@ class MSASpecial : MSAInst {
let Inst{31-26} = 0b000000;
}
+class MSA64Special : MSA64Inst {
+ let Inst{31-26} = 0b000000;
+}
+
class MSAPseudo<dag outs, dag ins, list<dag> pattern,
InstrItinClass itin = IIPseudo>:
MipsPseudo<outs, ins, pattern, itin> {
@@ -445,3 +449,17 @@ class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial {
let Inst{7-6} = sa;
let Inst{5-0} = minor;
}
+
+class SPECIAL_DLSA_FMT<bits<6> minor>: MSA64Special {
+ bits<5> rs;
+ bits<5> rt;
+ bits<5> rd;
+ bits<2> sa;
+
+ let Inst{25-21} = rs;
+ let Inst{20-16} = rt;
+ let Inst{15-11} = rd;
+ let Inst{10-8} = 0b000;
+ let Inst{7-6} = sa;
+ let Inst{5-0} = minor;
+}