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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-05-09 16:42:16 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-05-09 16:42:16 +0000 |
| commit | 87b983680c5718e85ea9545fe34f0ec05e8b016a (patch) | |
| tree | 0ef14bda6b14f9f3f9a614d61dd6848328bc8821 /lib/Target/R600/R600ISelLowering.cpp | |
| parent | bfaccd494f8abcfd5db129235affa7219264bcee (diff) | |
| download | llvm-87b983680c5718e85ea9545fe34f0ec05e8b016a.tar.gz llvm-87b983680c5718e85ea9545fe34f0ec05e8b016a.tar.bz2 llvm-87b983680c5718e85ea9545fe34f0ec05e8b016a.tar.xz | |
R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208429 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600ISelLowering.cpp')
| -rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index b40cb6724d..e3bcab02e3 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -986,13 +986,6 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); } - - // Possible Min/Max pattern - SDValue MinMax = LowerMinMax(Op, DAG); - if (MinMax.getNode()) { - return MinMax; - } - // If we make it this for it means we have no native instructions to handle // this SELECT_CC, so we must lower it. SDValue HWTrue, HWFalse; @@ -1672,6 +1665,11 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N, } case ISD::SELECT_CC: { + // Try common optimizations + SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI); + if (Ret.getNode()) + return Ret; + // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq -> // selectcc x, y, a, b, inv(cc) // |