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| author | Chris Lattner <sabre@nondot.org> | 2006-05-04 18:16:01 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-05-04 18:16:01 +0000 |
| commit | 8b915b4ed2c6e43413937ac71c0cbcf476ad1a98 (patch) | |
| tree | dc4cddca818202794ae10be1bf2bad36c8a6f344 /lib/Target/X86/X86InstrBuilder.h | |
| parent | 2d90ac7ca6117d3b160dde8a4f322c1079a6ffce (diff) | |
| download | llvm-8b915b4ed2c6e43413937ac71c0cbcf476ad1a98.tar.gz llvm-8b915b4ed2c6e43413937ac71c0cbcf476ad1a98.tar.bz2 llvm-8b915b4ed2c6e43413937ac71c0cbcf476ad1a98.tar.xz | |
Remove and simplify some more machineinstr/machineoperand stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28105 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrBuilder.h')
| -rw-r--r-- | lib/Target/X86/X86InstrBuilder.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h index 91a1069757..f3e1c28e4d 100644 --- a/lib/Target/X86/X86InstrBuilder.h +++ b/lib/Target/X86/X86InstrBuilder.h @@ -61,7 +61,7 @@ inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { // Because memory references are always represented with four // values, this adds: Reg, [1, NoReg, 0] to the instruction. - return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(0); + return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0); } @@ -71,14 +71,14 @@ inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB, /// inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, int Offset) { - return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(Offset); + return MIB.addReg(Reg).addImm(1).addReg(0).addImm(Offset); } /// addRegReg - This function is used to add a memory reference of the form: /// [Reg + Reg]. inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, unsigned Reg2) { - return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addImm(0); + return MIB.addReg(Reg1).addImm(1).addReg(Reg2).addImm(0); } inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB, @@ -91,7 +91,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB, MIB.addFrameIndex(AM.Base.FrameIndex); else assert (0); - MIB.addZImm(AM.Scale).addReg(AM.IndexReg); + MIB.addImm(AM.Scale).addReg(AM.IndexReg); if (AM.GV) return MIB.addGlobalAddress(AM.GV, AM.Disp); else @@ -105,7 +105,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB, /// inline const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) { - return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addImm(Offset); + return MIB.addFrameIndex(FI).addImm(1).addReg(0).addImm(Offset); } /// addConstantPoolReference - This function is used to add a reference to the @@ -117,7 +117,7 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) { inline const MachineInstrBuilder & addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, int Offset = 0) { - return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addImm(Offset); + return MIB.addConstantPoolIndex(CPI).addImm(1).addReg(0).addImm(Offset); } } // End llvm namespace |