Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph

and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8

10 files changed, 10 insertions, 10 deletions

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 537f6faf78..fcb100ae66 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -46,7 +46,7 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
 
 public:
   explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
-    : SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
+    : SelectionDAGISel(tm), TM(tm),
     Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
   }
 
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 801db44faf..49b52a0de5 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -143,7 +143,7 @@ namespace {
 
   public:
     explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
-      : SelectionDAGISel(*TM.getTargetLowering())
+      : SelectionDAGISel(TM)
     {}
 
     /// getI64Imm - Return a target constant with the specified value, of type
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 1f00bacb5e..858802cbb2 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -227,7 +227,7 @@ class SPUDAGToDAGISel :
 
 public:
   explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
-    SelectionDAGISel(*tm.getTargetLowering()),
+    SelectionDAGISel(tm),
     TM(tm),
     SPUtli(*tm.getTargetLowering())
   {}
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 4532ed2623..cdaa802853 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -38,7 +38,7 @@ namespace {
     unsigned GlobalBaseReg;
   public:
     explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
-      : SelectionDAGISel(*TM.getTargetLowering()) {}
+      : SelectionDAGISel(TM) {}
     
     virtual bool runOnFunction(Function &Fn) {
       // Make sure we re-emit a set of the global base reg if necessary
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 099fb53fae..768ab65892 100644
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -55,7 +55,7 @@ class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
  
 public:
   explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
-  SelectionDAGISel(*tm.getTargetLowering()),
+  SelectionDAGISel(tm),
   TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
   
   virtual void InstructionSelect();
diff --git a/lib/Target/PIC16/PIC16ISelDAGToDAG.h b/lib/Target/PIC16/PIC16ISelDAGToDAG.h
index 177313372b..83abed3958 100644
--- a/lib/Target/PIC16/PIC16ISelDAGToDAG.h
+++ b/lib/Target/PIC16/PIC16ISelDAGToDAG.h
@@ -35,7 +35,7 @@ class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
 
 public:
   explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) : 
-        SelectionDAGISel(PIC16Lowering),
+        SelectionDAGISel(tm),
         TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
   
   // Pass Name
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index fdbd126e78..a86604b1aa 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -44,7 +44,7 @@ namespace {
     unsigned GlobalBaseReg;
   public:
     explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
-      : SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
+      : SelectionDAGISel(tm), TM(tm),
         PPCLowering(*TM.getTargetLowering()),
         PPCSubTarget(*TM.getSubtargetImpl()) {}
     
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 34846529b2..12ed94cba6 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -34,7 +34,7 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
   const SparcSubtarget &Subtarget;
 public:
   explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
-    : SelectionDAGISel(*TM.getTargetLowering()),
+    : SelectionDAGISel(TM),
       Subtarget(TM.getSubtarget<SparcSubtarget>()) {
   }
 
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 907aa69206..44c43a2ef8 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -126,7 +126,7 @@ namespace {
 
   public:
     X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
-      : SelectionDAGISel(*tm.getTargetLowering(), fast),
+      : SelectionDAGISel(tm, fast),
         TM(tm), X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()),
         OptForSize(false) {}
diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 684ef0bf12..36d76ef571 100644
--- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -42,7 +42,7 @@ namespace {
 
   public:
     XCoreDAGToDAGISel(XCoreTargetMachine &TM)
-      : SelectionDAGISel(*TM.getTargetLowering()),
+      : SelectionDAGISel(TM),
         Lowering(*TM.getTargetLowering()), 
         Subtarget(*TM.getSubtargetImpl()) { }