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authorAkira Hatanaka <ahatanaka@mips.com>2012-11-16 02:39:34 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-11-16 02:39:34 +0000
commita032dbd62f46a40b2cf759ce0dd0ebd41ef0614c (patch)
tree1526a67e09837250eaa27e9da8776f1710166ad3 /lib/Target
parent96952bd3b10d6a880b406461e2373b8781abc919 (diff)
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[mips] Fix delay slot filler so that instructions with register operand $1 are
allowed in branch delay slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168131 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/Mips/MipsDelaySlotFiller.cpp51
1 files changed, 34 insertions, 17 deletions
diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index e3c8ed75cf..17a19fb2ab 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -231,31 +231,48 @@ bool Filler::delayHasHazard(InstrIter candidate,
return false;
}
+// Helper function for getting a MachineOperand's register number and adding it
+// to RegDefs or RegUses.
+static void insertDefUse(const MachineOperand &MO,
+ SmallSet<unsigned, 32> &RegDefs,
+ SmallSet<unsigned, 32> &RegUses,
+ unsigned ExcludedReg = 0) {
+ unsigned Reg;
+
+ if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
+ return;
+
+ if (MO.isDef())
+ RegDefs.insert(Reg);
+ else if (MO.isUse())
+ RegUses.insert(Reg);
+}
+
// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
void Filler::insertDefsUses(InstrIter MI,
SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses) {
- // If MI is a call or return, just examine the explicit non-variadic operands.
- MCInstrDesc MCID = MI->getDesc();
- unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
- MI->getNumOperands();
+ unsigned I, E = MI->getDesc().getNumOperands();
- // Add RA to RegDefs to prevent users of RA from going into delay slot.
- if (MI->isCall())
- RegDefs.insert(Mips::RA);
+ for (I = 0; I != E; ++I)
+ insertDefUse(MI->getOperand(I), RegDefs, RegUses);
- for (unsigned i = 0; i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- unsigned Reg;
+ // If MI is a call, add RA to RegDefs to prevent users of RA from going into
+ // delay slot.
+ if (MI->isCall()) {
+ RegDefs.insert(Mips::RA);
+ return;
+ }
- if (!MO.isReg() || !(Reg = MO.getReg()))
- continue;
+ // Return if MI is a return.
+ if (MI->isReturn())
+ return;
- if (MO.isDef())
- RegDefs.insert(Reg);
- else if (MO.isUse())
- RegUses.insert(Reg);
- }
+ // Examine the implicit operands. Exclude register AT which is in the list of
+ // clobbered registers of branch instructions.
+ E = MI->getNumOperands();
+ for (; I != E; ++I)
+ insertDefUse(MI->getOperand(I), RegDefs, RegUses, Mips::AT);
}
//returns true if the Reg or its alias is in the RegSet.