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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-23 18:00:55 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-23 18:00:55 +0000 |
commit | 791c05439133c845d446e8c315549969ba292d14 (patch) | |
tree | daded37cd5d43838f082193b78d2d2d3fecf26d5 /lib | |
parent | 627230239477e2cdf6e74d9fb7523b38341b24f6 (diff) | |
download | llvm-791c05439133c845d446e8c315549969ba292d14.tar.gz llvm-791c05439133c845d446e8c315549969ba292d14.tar.bz2 llvm-791c05439133c845d446e8c315549969ba292d14.tar.xz |
R600: Remove AMDILISelLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211519 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.cpp | 7 | ||||
-rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.h | 6 | ||||
-rw-r--r-- | lib/Target/R600/AMDILISelLowering.cpp | 35 | ||||
-rw-r--r-- | lib/Target/R600/CMakeLists.txt | 1 | ||||
-rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 11 | ||||
-rw-r--r-- | lib/Target/R600/R600ISelLowering.h | 1 |
6 files changed, 13 insertions, 48 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index 0cfbf6bcf1..6ff1703c91 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -108,9 +108,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : Subtarget = &TM.getSubtarget<AMDGPUSubtarget>(); - // Initialize target lowering borrowed from AMDIL - InitAMDILLowering(); - setOperationAction(ISD::Constant, MVT::i32, Legal); setOperationAction(ISD::Constant, MVT::i64, Legal); setOperationAction(ISD::ConstantFP, MVT::f32, Legal); @@ -518,7 +515,6 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, llvm_unreachable("Custom lowering code for this" "instruction is not implemented yet!"); break; - // AMDGPU DAG lowering. case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); @@ -534,9 +530,6 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); - - // AMDIL DAG lowering. - case ISD::BRCOND: return LowerBRCOND(Op, DAG); } return Op; } diff --git a/lib/Target/R600/AMDGPUISelLowering.h b/lib/Target/R600/AMDGPUISelLowering.h index cffa6bc48f..874aa978b5 100644 --- a/lib/Target/R600/AMDGPUISelLowering.h +++ b/lib/Target/R600/AMDGPUISelLowering.h @@ -113,6 +113,7 @@ public: bool isNarrowingProfitable(EVT VT1, EVT VT2) const override; MVT getVectorIdxTy() const override; + bool isSelectSupported(SelectSupportKind) const override; bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; bool ShouldShrinkFPConstant(EVT VT) const override; @@ -155,11 +156,6 @@ public: SDValue Op, const SelectionDAG &DAG, unsigned Depth = 0) const override; - -private: - // Functions defined in AMDILISelLowering.cpp - void InitAMDILLowering(); - SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; }; namespace AMDGPUISD { diff --git a/lib/Target/R600/AMDILISelLowering.cpp b/lib/Target/R600/AMDILISelLowering.cpp deleted file mode 100644 index bbf3b3b60e..0000000000 --- a/lib/Target/R600/AMDILISelLowering.cpp +++ /dev/null @@ -1,35 +0,0 @@ -//===-- AMDILISelLowering.cpp - AMDIL DAG Lowering Implementation ---------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// -/// \file -/// \brief TargetLowering functions borrowed from AMDIL. -// -//===----------------------------------------------------------------------===// - -#include "AMDGPUISelLowering.h" -#include "llvm/CodeGen/SelectionDAG.h" - -using namespace llvm; - -//===----------------------------------------------------------------------===// -// TargetLowering Class Implementation Begins -//===----------------------------------------------------------------------===// -void AMDGPUTargetLowering::InitAMDILLowering() { - setOperationAction(ISD::BRCOND, MVT::Other, Custom); - setSelectIsExpensive(true); // FIXME: This makes no sense at all -} - -SDValue AMDGPUTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { - SDValue Chain = Op.getOperand(0); - SDValue Cond = Op.getOperand(1); - SDValue Jump = Op.getOperand(2); - - return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(), - Chain, Jump, Cond); -} diff --git a/lib/Target/R600/CMakeLists.txt b/lib/Target/R600/CMakeLists.txt index c39068c683..dc1fa9f557 100644 --- a/lib/Target/R600/CMakeLists.txt +++ b/lib/Target/R600/CMakeLists.txt @@ -13,7 +13,6 @@ add_public_tablegen_target(AMDGPUCommonTableGen) add_llvm_target(R600CodeGen AMDILCFGStructurizer.cpp - AMDILISelLowering.cpp AMDGPUAsmPrinter.cpp AMDGPUFrameLowering.cpp AMDGPUIntrinsicInfo.cpp diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index 612268a58b..13d555e7e1 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -68,6 +68,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : setOperationAction(ISD::BR_CC, MVT::i32, Expand); setOperationAction(ISD::BR_CC, MVT::f32, Expand); + setOperationAction(ISD::BRCOND, MVT::Other, Custom); setOperationAction(ISD::FSUB, MVT::f32, Expand); @@ -578,6 +579,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); case ISD::STORE: return LowerSTORE(Op, DAG); case ISD::LOAD: return LowerLOAD(Op, DAG); + case ISD::BRCOND: return LowerBRCOND(Op, DAG); case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG); case ISD::INTRINSIC_VOID: { SDValue Chain = Op.getOperand(0); @@ -1645,6 +1647,15 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const return DAG.getMergeValues(Ops, DL); } +SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { + SDValue Chain = Op.getOperand(0); + SDValue Cond = Op.getOperand(1); + SDValue Jump = Op.getOperand(2); + + return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(), + Chain, Jump, Cond); +} + /// XXX Only kernel functions are supported, so we can assume for now that /// every function is a kernel function, but in the future we should use /// separate calling conventions for kernel and non-kernel functions. diff --git a/lib/Target/R600/R600ISelLowering.h b/lib/Target/R600/R600ISelLowering.h index 381642aa60..d22c8c98a5 100644 --- a/lib/Target/R600/R600ISelLowering.h +++ b/lib/Target/R600/R600ISelLowering.h @@ -59,6 +59,7 @@ private: SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const; |