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| author | Andrew Trick <atrick@apple.com> | 2012-02-08 21:23:03 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-02-08 21:23:03 +0000 |
| commit | 9d41bd5c78b99750d820e01bcd4a4e479b713d4c (patch) | |
| tree | e55b6338a6cf3b62e035e6dafd95789a4f139d13 /lib | |
| parent | 9f17cf625dc8be1e92cd2755e2d118ce38fc7268 (diff) | |
| download | llvm-9d41bd5c78b99750d820e01bcd4a4e479b713d4c.tar.gz llvm-9d41bd5c78b99750d820e01bcd4a4e479b713d4c.tar.bz2 llvm-9d41bd5c78b99750d820e01bcd4a4e479b713d4c.tar.xz | |
Move pass configuration out of pass constructors: MachineLICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150099 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/MachineLICM.cpp | 9 | ||||
| -rw-r--r-- | lib/CodeGen/Passes.cpp | 2 |
2 files changed, 6 insertions, 5 deletions
diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp index 7c07ac4a24..bf6185a7ea 100644 --- a/lib/CodeGen/MachineLICM.cpp +++ b/lib/CodeGen/MachineLICM.cpp @@ -60,8 +60,6 @@ STATISTIC(NumPostRAHoisted, namespace { class MachineLICM : public MachineFunctionPass { - bool PreRegAlloc; - const TargetMachine *TM; const TargetInstrInfo *TII; const TargetLowering *TLI; @@ -69,6 +67,7 @@ namespace { const MachineFrameInfo *MFI; MachineRegisterInfo *MRI; const InstrItineraryData *InstrItins; + bool PreRegAlloc; // Various analyses that we use... AliasAnalysis *AA; // Alias analysis info. @@ -298,8 +297,8 @@ INITIALIZE_AG_DEPENDENCY(AliasAnalysis) INITIALIZE_PASS_END(MachineLICM, "machinelicm", "Machine Loop Invariant Code Motion", false, false) -FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) { - return new MachineLICM(PreRegAlloc); +FunctionPass *llvm::createMachineLICMPass() { + return new MachineLICM(); } /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most @@ -332,6 +331,8 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) { MRI = &MF.getRegInfo(); InstrItins = TM->getInstrItineraryData(); + PreRegAlloc = MRI->isSSA(); + if (PreRegAlloc) { // Estimate register pressure during pre-regalloc pass. unsigned NumRC = TRI->getNumRegClasses(); diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp index 01662743af..354fedbef9 100644 --- a/lib/CodeGen/Passes.cpp +++ b/lib/CodeGen/Passes.cpp @@ -244,7 +244,7 @@ void TargetPassConfig::addMachinePasses() { // Run post-ra machine LICM to hoist reloads / remats. if (!DisablePostRAMachineLICM) - PM.add(createMachineLICMPass(false)); + PM.add(createMachineLICMPass()); printAndVerify("After StackSlotColoring and postra Machine LICM"); } |