Removed tabs everywhere except autogenerated & external files. Add make

target for tabs checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8

31 files changed, 358 insertions, 348 deletions

diff --git a/lib/Analysis/IPA/CallGraphSCCPass.cpp b/lib/Analysis/IPA/CallGraphSCCPass.cpp
index fcf4202826..0640b63e6b 100644
--- a/lib/Analysis/IPA/CallGraphSCCPass.cpp
+++ b/lib/Analysis/IPA/CallGraphSCCPass.cpp
@@ -82,8 +82,7 @@ bool CGPassManager::runOnModule(Module &M) {
        I != E; ++I) {
 
     // Run all passes on current SCC
-    for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {  
-
+    for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
       Pass *P = getContainedPass(Index);
       AnalysisUsage AnUsage;
       P->getAnalysisUsage(AnUsage);
@@ -95,20 +94,20 @@ bool CGPassManager::runOnModule(Module &M) {
 
       StartPassTimer(P);
       if (CallGraphSCCPass *CGSP = dynamic_cast<CallGraphSCCPass *>(P))
-	Changed |= CGSP->runOnSCC(*I);   // TODO : What if CG is changed ?
+        Changed |= CGSP->runOnSCC(*I);   // TODO : What if CG is changed ?
       else {
-	FPPassManager *FPP = dynamic_cast<FPPassManager *>(P);
-	assert (FPP && "Invalid CGPassManager member");
-
-	// Run pass P on all functions current SCC
-	std::vector<CallGraphNode*> &SCC = *I;
-	for (unsigned i = 0, e = SCC.size(); i != e; ++i) {
-	  Function *F = SCC[i]->getFunction();
-	  if (F) {
+        FPPassManager *FPP = dynamic_cast<FPPassManager *>(P);
+        assert (FPP && "Invalid CGPassManager member");
+
+        // Run pass P on all functions current SCC
+        std::vector<CallGraphNode*> &SCC = *I;
+        for (unsigned i = 0, e = SCC.size(); i != e; ++i) {
+          Function *F = SCC[i]->getFunction();
+          if (F) {
             dumpPassInfo(P, EXECUTION_MSG, ON_FUNCTION_MSG, F->getName());
             Changed |= FPP->runOnFunction(*F);
           }
-	}
+        }
       }
       StopPassTimer(P);
 
@@ -149,7 +148,7 @@ bool CGPassManager::doFinalization(CallGraph &CG) {
 
 /// Assign pass manager to manage this pass.
 void CallGraphSCCPass::assignPassManager(PMStack &PMS,
-					 PassManagerType PreferredType) {
+                                         PassManagerType PreferredType) {
   // Find CGPassManager 
   while (!PMS.empty()) {
     if (PMS.top()->getPassManagerType() > PMT_CallGraphPassManager)
diff --git a/lib/CodeGen/MachOWriter.h b/lib/CodeGen/MachOWriter.h
index 061213a8c8..0792ac8a7d 100644
--- a/lib/CodeGen/MachOWriter.h
+++ b/lib/CodeGen/MachOWriter.h
@@ -254,19 +254,19 @@ namespace llvm {
       // The following constants are getting pulled in by one of the
       // system headers, which creates a neat clash with the enum.
 #if !defined(VM_PROT_NONE)
-#define VM_PROT_NONE		0x00
+#define VM_PROT_NONE    0x00
 #endif
 #if !defined(VM_PROT_READ)
-#define VM_PROT_READ		0x01
+#define VM_PROT_READ    0x01
 #endif
 #if !defined(VM_PROT_WRITE)
-#define VM_PROT_WRITE		0x02
+#define VM_PROT_WRITE   0x02
 #endif
 #if !defined(VM_PROT_EXECUTE)
-#define VM_PROT_EXECUTE		0x04
+#define VM_PROT_EXECUTE 0x04
 #endif
 #if !defined(VM_PROT_ALL)
-#define VM_PROT_ALL		0x07
+#define VM_PROT_ALL     0x07
 #endif
 
       // Constants for the vm protection fields
diff --git a/lib/CodeGen/README.txt b/lib/CodeGen/README.txt
index aa5a54c3ba..8e6b0a5e46 100644
--- a/lib/CodeGen/README.txt
+++ b/lib/CodeGen/README.txt
@@ -2,29 +2,29 @@
 
 Common register allocation / spilling problem:
 
-	mul lr, r4, lr
-	str lr, [sp, #+52]
-	ldr lr, [r1, #+32]
-	sxth r3, r3
-	ldr r4, [sp, #+52]
-	mla r4, r3, lr, r4
+        mul lr, r4, lr
+        str lr, [sp, #+52]
+        ldr lr, [r1, #+32]
+        sxth r3, r3
+        ldr r4, [sp, #+52]
+        mla r4, r3, lr, r4
 
 can be:
 
-	mul lr, r4, lr
+        mul lr, r4, lr
         mov r4, lr
-	str lr, [sp, #+52]
-	ldr lr, [r1, #+32]
-	sxth r3, r3
-	mla r4, r3, lr, r4
+        str lr, [sp, #+52]
+        ldr lr, [r1, #+32]
+        sxth r3, r3
+        mla r4, r3, lr, r4
 
 and then "merge" mul and mov:
 
-	mul r4, r4, lr
-	str lr, [sp, #+52]
-	ldr lr, [r1, #+32]
-	sxth r3, r3
-	mla r4, r3, lr, r4
+        mul r4, r4, lr
+        str lr, [sp, #+52]
+        ldr lr, [r1, #+32]
+        sxth r3, r3
+        mla r4, r3, lr, r4
 
 It also increase the likelyhood the store may become dead.
 
@@ -70,13 +70,13 @@ Some potential added complexities:
 
 bb27 ...
         ...
-	%reg1037 = ADDri %reg1039, 1
-	%reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
+        %reg1037 = ADDri %reg1039, 1
+        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
     Successors according to CFG: 0x8b03bf0 (#5)
 
 bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
     Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
-	%reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
+        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
 
 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
 operand of the PHI node in bb76 and its operand %reg1039 is the result of the
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
index e4133cec6e..c6187f1109 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
@@ -288,9 +288,9 @@ private:
                                         // Tally iterator 
   
   /// SlotsAvailable - Returns true if all units are available.
-	///
+  ///
   bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
-                                              unsigned &Resource) {
+                      unsigned &Resource) {
     assert(N && "Must check availability with N != 0");
     // Determine end of interval
     Iter End = Begin + N;
@@ -318,23 +318,23 @@ private:
     Resource = 0;
     return false;
   }
-	
-	/// RetrySlot - Finds a good candidate slot to retry search.
+  
+  /// RetrySlot - Finds a good candidate slot to retry search.
   Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
     assert(N && "Must check availability with N != 0");
     // Determine end of interval
     Iter End = Begin + N;
     assert(End <= Tally.end() && "Tally is not large enough for schedule");
-		
-		while (Begin != End--) {
-			// Clear units in use
-			ResourceSet &= ~*End;
-			// If no units left then we should go no further 
-			if (!ResourceSet) return End + 1;
-		}
-		// Made it all the way through
-		return Begin;
-	}
+    
+    while (Begin != End--) {
+      // Clear units in use
+      ResourceSet &= ~*End;
+      // If no units left then we should go no further 
+      if (!ResourceSet) return End + 1;
+    }
+    // Made it all the way through
+    return Begin;
+  }
   
   /// FindAndReserveStages - Return true if the stages can be completed. If
   /// so mark as busy.
@@ -391,13 +391,13 @@ public:
   // FindAndReserve - Locate an ideal slot for the specified stages and mark
   // as busy.
   unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
-                                         InstrStage *StageEnd) {
-		// Where to begin 
-		Iter Begin = Tally.begin() + Slot;
-		// Find a free slot
-		Iter Where = FindSlots(Begin, StageBegin, StageEnd);
-		// Distance is slot number
-		unsigned Final = Where - Tally.begin();
+                          InstrStage *StageEnd) {
+    // Where to begin 
+    Iter Begin = Tally.begin() + Slot;
+    // Find a free slot
+    Iter Where = FindSlots(Begin, StageBegin, StageEnd);
+    // Distance is slot number
+    unsigned Final = Where - Tally.begin();
     return Final;
   }
 
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index d72c6eb01d..7d30062995 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2150,7 +2150,7 @@ static mu magicu64(uint64_t d)
 /// multiplying by a magic number.  See:
 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 
-				    std::vector<SDNode*>* Created) const {
+                                    std::vector<SDNode*>* Created) const {
   MVT::ValueType VT = N->getValueType(0);
   
   // Check to see if we can do this.
@@ -2198,7 +2198,7 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
 /// multiplying by a magic number.  See:
 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
-				    std::vector<SDNode*>* Created) const {
+                                    std::vector<SDNode*>* Created) const {
   MVT::ValueType VT = N->getValueType(0);
   
   // Check to see if we can do this.
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 6058be114e..2b0450b971 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -53,8 +53,8 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
   case ARM::MOVr:
   case ARM::tMOVr:
     assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() &&
-	   MI.getOperand(1).isRegister() &&
-	   "Invalid ARM MOV instruction");
+           MI.getOperand(1).isRegister() &&
+           "Invalid ARM MOV instruction");
     SrcReg = MI.getOperand(1).getReg();
     DstReg = MI.getOperand(0).getReg();
     return true;
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index bf6adbd95f..09420071bf 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -1372,7 +1372,7 @@ static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
 }
 
 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
-				   MachineBasicBlock &MBB) const {
+                                   MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
   assert((MBBI->getOpcode() == ARM::BX_RET ||
           MBBI->getOpcode() == ARM::tBX_RET ||
diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 18ff6babf5..0494777aab 100644
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -53,9 +53,9 @@ namespace {
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          unsigned AsmVariant, const char *ExtraCode);
     bool PrintAsmMemoryOperand(const MachineInstr *MI, 
-			       unsigned OpNo,
-			       unsigned AsmVariant, 
-			       const char *ExtraCode);
+                               unsigned OpNo,
+                               unsigned AsmVariant, 
+                               const char *ExtraCode);
   };
 } // end of anonymous namespace
 
@@ -278,16 +278,16 @@ bool AlphaAsmPrinter::doFinalization(Module &M) {
 /// PrintAsmOperand - Print out an operand for an inline asm expression.
 ///
 bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
-                                    unsigned AsmVariant, 
-                                    const char *ExtraCode) {
+                                      unsigned AsmVariant, 
+                                      const char *ExtraCode) {
   printOperand(MI, OpNo);
   return false;
 }
 
 bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 
-					    unsigned OpNo,
-					    unsigned AsmVariant, 
-					    const char *ExtraCode) {
+                                            unsigned OpNo,
+                                            unsigned AsmVariant, 
+                                            const char *ExtraCode) {
   if (ExtraCode && ExtraCode[0])
     return true; // Unknown modifier.
   O << "0(";
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 14da957333..2f1eb48068 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -50,7 +50,7 @@ namespace {
     static int64_t get_ldah16(int64_t x) {
       int64_t y = x / IMM_MULT;
       if (x % IMM_MULT > IMM_HIGH)
-	++y;
+        ++y;
       return y;
     }
 
@@ -145,7 +145,7 @@ namespace {
   public:
     AlphaDAGToDAGISel(TargetMachine &TM)
       : SelectionDAGISel(AlphaLowering), 
-	AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering())) 
+        AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering())) 
     {}
 
     /// getI64Imm - Return a target constant with the specified value, of type
@@ -177,7 +177,7 @@ namespace {
       default: return true;
       case 'm':   // memory
         Op0 = Op;
-	AddToISelQueue(Op0);
+        AddToISelQueue(Op0);
         break;
       }
       
@@ -203,7 +203,7 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
   MachineFunction* MF = BB->getParent();
   unsigned GP = 0;
   for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
-	ee = MF->livein_end(); ii != ee; ++ii)
+        ee = MF->livein_end(); ii != ee; ++ii)
     if (ii->first == Alpha::R29) {
       GP = ii->second;
       break;
@@ -219,7 +219,7 @@ SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
   MachineFunction* MF = BB->getParent();
   unsigned RA = 0;
   for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
-	ee = MF->livein_end(); ii != ee; ++ii)
+        ee = MF->livein_end(); ii != ee; ++ii)
     if (ii->first == Alpha::R26) {
       RA = ii->second;
       break;
@@ -283,16 +283,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
     AddToISelQueue(N1);
     AddToISelQueue(N2);
     Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1, 
-				 SDOperand(0,0));
+                                 SDOperand(0,0));
     Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2, 
-				 Chain.getValue(1));
+                                 Chain.getValue(1));
     Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, 
-				 Chain.getValue(1));
+                                 Chain.getValue(1));
     SDNode *CNode =
       CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, 
                             Chain, Chain.getValue(1));
     Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, 
-				  SDOperand(CNode, 1));
+                                   SDOperand(CNode, 1));
     return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
   }
 
@@ -316,11 +316,11 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
     int64_t val = (int64_t)uval;
     int32_t val32 = (int32_t)val;
     if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
-	val >= IMM_LOW  + IMM_LOW  * IMM_MULT)
+        val >= IMM_LOW  + IMM_LOW  * IMM_MULT)
       break; //(LDAH (LDA))
     if ((uval >> 32) == 0 && //empty upper bits
-	val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
-      //	val32 >= IMM_LOW  + IMM_LOW  * IMM_MULT) //always true
+        val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
+      // val32 >= IMM_LOW  + IMM_LOW  * IMM_MULT) //always true
       break; //(zext (LDAH (LDA)))
     //Else use the constant pool
     ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
@@ -328,7 +328,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
     SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
                                         getGlobalBaseReg());
     return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, 
-                            CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
+                                CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
   }
   case ISD::TargetConstantFP: {
     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
@@ -358,21 +358,21 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
       switch(CC) {
       default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
       case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
-	Opc = Alpha::CMPTEQ; break;
+        Opc = Alpha::CMPTEQ; break;
       case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: 
-	Opc = Alpha::CMPTLT; break;
+        Opc = Alpha::CMPTLT; break;
       case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: 
-	Opc = Alpha::CMPTLE; break;
+        Opc = Alpha::CMPTLE; break;
       case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: 
-	Opc = Alpha::CMPTLT; rev = true; break;
+        Opc = Alpha::CMPTLT; rev = true; break;
       case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: 
-	Opc = Alpha::CMPTLE; rev = true; break;
+        Opc = Alpha::CMPTLE; rev = true; break;
       case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
-	Opc = Alpha::CMPTEQ; inv = true; break;
+        Opc = Alpha::CMPTEQ; inv = true; break;
       case ISD::SETO:
-	Opc = Alpha::CMPTUN; inv = true; break;
+        Opc = Alpha::CMPTUN; inv = true; break;
       case ISD::SETUO:
-	Opc = Alpha::CMPTUN; break;
+        Opc = Alpha::CMPTUN; break;
       };
       SDOperand tmp1 = N->getOperand(rev?1:0);
       SDOperand tmp2 = N->getOperand(rev?0:1);
@@ -385,12 +385,13 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
       switch(CC) {
       case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
       case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
-	{
-	  SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64, tmp1, tmp2);
-	  cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64, 
-				      SDOperand(cmp2, 0), SDOperand(cmp, 0));
-	  break;
-	}
+       {
+         SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
+                                              tmp1, tmp2);
+         cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64, 
+                                     SDOperand(cmp2, 0), SDOperand(cmp, 0));
+         break;
+       }
       default: break;
       }
 
@@ -403,8 +404,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
 
   case ISD::SELECT:
     if (MVT::isFloatingPoint(N->getValueType(0)) &&
-	(N->getOperand(0).getOpcode() != ISD::SETCC ||
-	 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
+        (N->getOperand(0).getOpcode() != ISD::SETCC ||
+         !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
       //This should be the condition not covered by the Patterns
       //FIXME: Don't have SelectCode die, but rather return something testable
       // so that things like this can be caught in fall though code
@@ -427,32 +428,31 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
     ConstantSDNode* SC = NULL;
     ConstantSDNode* MC = NULL;
     if (N->getOperand(0).getOpcode() == ISD::SRL &&
-	(MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
-	(SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
-      {
-	uint64_t sval = SC->getValue();
-	uint64_t mval = MC->getValue();
-        // If the result is a zap, let the autogened stuff handle it.
-	if (get_zapImm(N->getOperand(0), mval))
-	  break;
-	// given mask X, and shift S, we want to see if there is any zap in the
-        // mask if we play around with the botton S bits
-	uint64_t dontcare = (~0ULL) >> (64 - sval);
-	uint64_t mask = mval << sval;
-
-	if (get_zapImm(mask | dontcare))
-	  mask = mask | dontcare;
-
-	if (get_zapImm(mask)) {
-	  AddToISelQueue(N->getOperand(0).getOperand(0));
-	  SDOperand Z = 
-	    SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
-                                            N->getOperand(0).getOperand(0),
-					    getI64Imm(get_zapImm(mask))), 0);
-	  return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z, 
-                                       getI64Imm(sval));
-	}
+        (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
+        (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
+      uint64_t sval = SC->getValue();
+      uint64_t mval = MC->getValue();
+      // If the result is a zap, let the autogened stuff handle it.
+      if (get_zapImm(N->getOperand(0), mval))
+        break;
+      // given mask X, and shift S, we want to see if there is any zap in the
+      // mask if we play around with the botton S bits
+      uint64_t dontcare = (~0ULL) >> (64 - sval);
+      uint64_t mask = mval << sval;
+      
+      if (get_zapImm(mask | dontcare))
+        mask = mask | dontcare;
+      
+      if (get_zapImm(mask)) {
+        AddToISelQueue(N->getOperand(0).getOperand(0));
+        SDOperand Z = 
+          SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
+                                          N->getOperand(0).getOperand(0),
+                                          getI64Imm(get_zapImm(mask))), 0);
+        return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z, 
+                                     getI64Imm(sval));
       }
+    }
     break;
   }
 
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 4f636dc8f9..d70fd2aab3 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -172,7 +172,7 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
   SDOperand Zero = DAG.getConstant(0, PtrVT);
   
   SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi,  MVT::i64, JTI,
-			     DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+                             DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
   SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
   return Lo;
 }
@@ -197,8 +197,8 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
 // //#define SP    $30
 
 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
-				       int &VarArgsBase,
-				       int &VarArgsOffset) {
+                                       int &VarArgsBase,
+                                       int &VarArgsOffset) {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   std::vector<SDOperand> ArgValues;
@@ -224,17 +224,17 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
         abort();
       case MVT::f64:
         args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], 
-				      &Alpha::F8RCRegClass);
+                                      &Alpha::F8RCRegClass);
         ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
         break;
       case MVT::f32:
         args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], 
-				      &Alpha::F4RCRegClass);
+                                      &Alpha::F4RCRegClass);
         ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
         break;
       case MVT::i64:
         args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo], 
-				    &Alpha::GPRCRegClass);
+                                    &Alpha::GPRCRegClass);
         ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
         break;
       }
@@ -286,9 +286,9 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
 
 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
   SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, 
-				    DAG.getNode(AlphaISD::GlobalRetAddr, 
-                                    MVT::i64),
-				    SDOperand());
+                                    DAG.getNode(AlphaISD::GlobalRetAddr, 
+                                                MVT::i64),
+                                    SDOperand());
   switch (Op.getNumOperands()) {
   default:
     assert(0 && "Do not know how to return this many arguments!");
@@ -306,7 +306,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
       ArgReg = Alpha::F0;
     }
     Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
-    if(DAG.getMachineFunction().liveout_empty())
+    if (DAG.getMachineFunction().liveout_empty())
       DAG.getMachineFunction().addLiveOut(ArgReg);
     break;
   }
@@ -387,8 +387,8 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default: assert(0 && "Wasn't expecting to be able to lower this!");
   case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, 
-							   VarArgsBase,
-							   VarArgsOffset);
+                                                           VarArgsBase,
+                                                           VarArgsOffset);
 
   case ISD::RET: return LowerRET(Op,DAG);
   case ISD::JumpTable: return LowerJumpTable(Op, DAG);
@@ -420,7 +420,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
     
     SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi,  MVT::i64, CPI,
-			       DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+                               DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
     SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
     return Lo;
   }
@@ -432,18 +432,18 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     //    if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
     if (GV->hasInternalLinkage()) {
       SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi,  MVT::i64, GA,
-				 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+                                DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
       SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
       return Lo;
     } else
       return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, 
-			 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+                         DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
   }
   case ISD::ExternalSymbol: {
     return DAG.getNode(AlphaISD::RelLit, MVT::i64, 
-		       DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
-						   ->getSymbol(), MVT::i64),
-		       DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+                       DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
+                                                   ->getSymbol(), MVT::i64),
+                       DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
   }
 
   case ISD::UREM:
@@ -452,8 +452,8 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     if (Op.getOperand(1).getOpcode() == ISD::Constant) {
       MVT::ValueType VT = Op.Val->getValueType(0);
       SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
-	BuildUDIV(Op.Val, DAG, NULL) :
-	BuildSDIV(Op.Val, DAG, NULL);
+        BuildUDIV(Op.Val, DAG, NULL) :
+        BuildSDIV(Op.Val, DAG, NULL);
       Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
       Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
       return Tmp1;
@@ -463,10 +463,10 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   case ISD::UDIV:
     if (MVT::isInteger(Op.getValueType())) {
       if (Op.getOperand(1).getOpcode() == ISD::Constant)
-	return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL) 
-	  : BuildUDIV(Op.Val, DAG, NULL);
+        return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL) 
+          : BuildUDIV(Op.Val, DAG, NULL);
       const char* opstr = 0;
-      switch(Op.getOpcode()) {
+      switch (Op.getOpcode()) {
       case ISD::UREM: opstr = "__remqu"; break;
       case ISD::SREM: opstr = "__remq";  break;
       case ISD::UDIV: opstr = "__divqu"; break;
@@ -591,29 +591,28 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
     default: break;  // Unknown constriant letter
     case 'f': 
       return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
-				   Alpha::F3 , Alpha::F4 , Alpha::F5 , 
-				   Alpha::F6 , Alpha::F7 , Alpha::F8 , 
-				   Alpha::F9 , Alpha::F10, Alpha::F11, 
+                                   Alpha::F3 , Alpha::F4 , Alpha::F5 ,
+                                   Alpha::F6 , Alpha::F7 , Alpha::F8 , 
+                                   Alpha::F9 , Alpha::F10, Alpha::F11, 
                                    Alpha::F12, Alpha::F13, Alpha::F14, 
-				   Alpha::F15, Alpha::F16, Alpha::F17, 
-				   Alpha::F18, Alpha::F19, Alpha::F20, 
-				   Alpha::F21, Alpha::F22, Alpha::F23, 
+                                   Alpha::F15, Alpha::F16, Alpha::F17, 
+                                   Alpha::F18, Alpha::F19, Alpha::F20, 
+                                   Alpha::F21, Alpha::F22, Alpha::F23, 
                                    Alpha::F24, Alpha::F25, Alpha::F26, 
-				   Alpha::F27, Alpha::F28, Alpha::F29, 
-				   Alpha::F30, Alpha::F31, 0);
+                                   Alpha::F27, Alpha::F28, Alpha::F29, 
+                                   Alpha::F30, Alpha::F31, 0);
     case 'r': 
       return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 , 
-				   Alpha::R3 , Alpha::R4 , Alpha::R5 , 
-				   Alpha::R6 , Alpha::R7 , Alpha::R8 , 
-				   Alpha::R9 , Alpha::R10, Alpha::R11, 
+                                   Alpha::R3 , Alpha::R4 , Alpha::R5 , 
+                                   Alpha::R6 , Alpha::R7 , Alpha::R8 , 
+                                   Alpha::R9 , Alpha::R10, Alpha::R11, 
                                    Alpha::R12, Alpha::R13, Alpha::R14, 
-				   Alpha::R15, Alpha::R16, Alpha::R17, 
-				   Alpha::R18, Alpha::R19, Alpha::R20, 
-				   Alpha::R21, Alpha::R22, Alpha::R23, 
+                                   Alpha::R15, Alpha::R16, Alpha::R17, 
+                                   Alpha::R18, Alpha::R19, Alpha::R20, 
+                                   Alpha::R21, Alpha::R22, Alpha::R23, 
                                    Alpha::R24, Alpha::R25, Alpha::R26, 
-				   Alpha::R27, Alpha::R28, Alpha::R29, 
-				   Alpha::R30, Alpha::R31, 0);
- 
+                                   Alpha::R27, Alpha::R28, Alpha::R29, 
+                                   Alpha::R30, Alpha::R31, 0);
     }
   }
   
diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index a5c984eaf6..6d2d243e3d 100644
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -50,101 +50,104 @@ namespace {
       unsigned count = 0;
       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
            FI != FE; ++FI) {
-	MachineBasicBlock& MBB = *FI;
-	bool ub = false;
-	  for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
-	    if (count%4 == 0)
-	      prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
-	    ++count;
-	    MachineInstr *MI = I++;
-	    switch (MI->getOpcode()) {
-	    case Alpha::LDQ:  case Alpha::LDL:
-	    case Alpha::LDWU: case Alpha::LDBU:
-	    case Alpha::LDT: case Alpha::LDS:
-	    case Alpha::STQ:  case Alpha::STL:
-	    case Alpha::STW:  case Alpha::STB:
-	    case Alpha::STT: case Alpha::STS:
-	      if (MI->getOperand(2).getReg() == Alpha::R30) {
-		if (prev[0] 
-		    && prev[0]->getOperand(2).getReg() == 
-		    MI->getOperand(2).getReg()
-		    && prev[0]->getOperand(1).getImmedValue() == 
-		    MI->getOperand(1).getImmedValue()) {
-		  prev[0] = prev[1];
-		  prev[1] = prev[2];
-		  prev[2] = 0;
-		  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-		    .addReg(Alpha::R31); 
-		  Changed = true; nopintro += 1;
-		  count += 1;
-		} else if (prev[1] 
-			   && prev[1]->getOperand(2).getReg() == 
-			   MI->getOperand(2).getReg()
-			   && prev[1]->getOperand(1).getImmedValue() == 
-			   MI->getOperand(1).getImmedValue()) {
-		  prev[0] = prev[2];
-		  prev[1] = prev[2] = 0;
-		  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-		    .addReg(Alpha::R31); 
-		  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-		    .addReg(Alpha::R31);
-		  Changed = true; nopintro += 2;
-		  count += 2;
-		} else if (prev[2] 
-                           && prev[2]->getOperand(2).getReg() == 
-                           MI->getOperand(2).getReg()
-                           && prev[2]->getOperand(1).getImmedValue() == 
-                           MI->getOperand(1).getImmedValue()) {
-                  prev[0] = prev[1] = prev[2] = 0;
-                  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                    .addReg(Alpha::R31);
-                  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                    .addReg(Alpha::R31);
-                  BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                    .addReg(Alpha::R31);
-                  Changed = true; nopintro += 3;
-                  count += 3;
-                }
-                prev[0] = prev[1];
-                prev[1] = prev[2];
-                prev[2] = MI;
-        	break;
-              }
-              prev[0] = prev[1];
-              prev[1] = prev[2];
-              prev[2] = 0;
-              break;
-            case Alpha::ALTENT:
-            case Alpha::MEMLABEL:
-            case Alpha::PCLABEL:
-            case Alpha::IDEF_I:
-            case Alpha::IDEF_F32:
-            case Alpha::IDEF_F64:
-              --count;
-              break;
-            case Alpha::BR:
-            case Alpha::JMP:
-              ub = true;
-              //fall through
-            default:
-              prev[0] = prev[1];
-              prev[1] = prev[2];
-              prev[2] = 0;
-              break;
-            }
+        MachineBasicBlock& MBB = *FI;
+        bool ub = false;
+        for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
+          if (count%4 == 0)
+            prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
+          ++count;
+          MachineInstr *MI = I++;
+          switch (MI->getOpcode()) {
+          case Alpha::LDQ:  case Alpha::LDL:
+          case Alpha::LDWU: case Alpha::LDBU:
+          case Alpha::LDT: case Alpha::LDS:
+          case Alpha::STQ:  case Alpha::STL:
+          case Alpha::STW:  case Alpha::STB:
+          case Alpha::STT: case Alpha::STS:
+           if (MI->getOperand(2).getReg() == Alpha::R30) {
+             if (prev[0] 
+                 && prev[0]->getOperand(2).getReg() == 
+                 MI->getOperand(2).getReg()
+                 && prev[0]->getOperand(1).getImmedValue() == 
+                 MI->getOperand(1).getImmedValue()) {
+               prev[0] = prev[1];
+               prev[1] = prev[2];
+               prev[2] = 0;
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31)
+                 .addReg(Alpha::R31); 
+               Changed = true; nopintro += 1;
+               count += 1;
+             } else if (prev[1] 
+                        && prev[1]->getOperand(2).getReg() == 
+                        MI->getOperand(2).getReg()
+                        && prev[1]->getOperand(1).getImmedValue() == 
+                        MI->getOperand(1).getImmedValue()) {
+               prev[0] = prev[2];
+               prev[1] = prev[2] = 0;
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31)
+                 .addReg(Alpha::R31); 
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31)
+                 .addReg(Alpha::R31);
+               Changed = true; nopintro += 2;
+               count += 2;
+             } else if (prev[2] 
+                        && prev[2]->getOperand(2).getReg() == 
+                        MI->getOperand(2).getReg()
+                        && prev[2]->getOperand(1).getImmedValue() == 
+                        MI->getOperand(1).getImmedValue()) {
+               prev[0] = prev[1] = prev[2] = 0;
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+                 .addReg(Alpha::R31);
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+                 .addReg(Alpha::R31);
+               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+                 .addReg(Alpha::R31);
+               Changed = true; nopintro += 3;
+               count += 3;
+             }
+             prev[0] = prev[1];
+             prev[1] = prev[2];
+             prev[2] = MI;
+             break;
+           }
+           prev[0] = prev[1];
+           prev[1] = prev[2];
+           prev[2] = 0;
+           break;
+          case Alpha::ALTENT:
+          case Alpha::MEMLABEL:
+          case Alpha::PCLABEL:
+          case Alpha::IDEF_I:
+          case Alpha::IDEF_F32:
+          case Alpha::IDEF_F64:
+            --count;
+            break;
+          case Alpha::BR:
+          case Alpha::JMP:
+            ub = true;
+            //fall through
+          default:
+            prev[0] = prev[1];
+            prev[1] = prev[2];
+            prev[2] = 0;
+            break;
           }
-          if (ub || AlignAll) {
-            //we can align stuff for free at this point
-            while (count % 4) {
-              BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
-                .addReg(Alpha::R31).addReg(Alpha::R31);
-              ++count;
-              ++nopalign;
-              prev[0] = prev[1];
-              prev[1] = prev[2];
-              prev[2] = 0;
-            }
+        }
+        if (ub || AlignAll) {
+          //we can align stuff for free at this point
+          while (count % 4) {
+            BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
+              .addReg(Alpha::R31).addReg(Alpha::R31);
+            ++count;
+            ++nopalign;
+            prev[0] = prev[1];
+            prev[1] = prev[2];
+            prev[2] = 0;
           }
+        }
       }
       return Changed;
     }
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 8dd8b1769a..717b5388e0 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -117,17 +117,17 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
    case Alpha::CPYST:
      if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
        if (OpNum == 0) {  // move -> store
-	 unsigned InReg = MI->getOperand(1).getReg();
-	 Opc = (Opc == Alpha::BISr) ? Alpha::STQ : 
-	   ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
-	 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
-	   .addReg(Alpha::F31);
+         unsigned InReg = MI->getOperand(1).getReg();
+         Opc = (Opc == Alpha::BISr) ? Alpha::STQ : 
+           ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
+         NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
+           .addReg(Alpha::F31);
        } else {           // load -> move
-	 unsigned OutReg = MI->getOperand(0).getReg();
-	 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : 
-	   ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
-	 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
-	   .addReg(Alpha::F31);
+         unsigned OutReg = MI->getOperand(0).getReg();
+         Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : 
+           ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
+         NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
+           .addReg(Alpha::F31);
        }
      }
      break;
diff --git a/lib/Target/IA64/IA64Bundling.cpp b/lib/Target/IA64/IA64Bundling.cpp
index 7e37df022d..08e4ba8d37 100644
--- a/lib/Target/IA64/IA64Bundling.cpp
+++ b/lib/Target/IA64/IA64Bundling.cpp
@@ -56,10 +56,10 @@ namespace {
       return Changed;
     }
 
-    std::set<unsigned> PendingRegWrites; // XXX: ugly global, but
-                         // pending writes can cross basic blocks. Note that
-                         // taken branches end instruction groups. So we
-			 // only need to worry about 'fallthrough' code
+    // XXX: ugly global, but pending writes can cross basic blocks. Note that
+    // taken branches end instruction groups. So we only need to worry about
+    // 'fallthrough' code
+    std::set<unsigned> PendingRegWrites;
   };
 } // end of anonymous namespace
 
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 6185d380b5..f71a3ea893 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -352,9 +352,10 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
     Chain = targetEntryPoint.getValue(1);
     SDOperand targetGPAddr=
       SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64, 
-		    FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
+                                      FnDescriptor,
+                                      CurDAG->getConstant(8, MVT::i64)), 0);
     Chain = targetGPAddr.getValue(1);
-    SDOperand targetGP=
+    SDOperand targetGP =
       SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
     Chain = targetGP.getValue(1);
 
@@ -418,14 +419,14 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     if (N->hasOneUse())
       return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
-                                 CurDAG->getTargetFrameIndex(FI, MVT::i64));
+                                  CurDAG->getTargetFrameIndex(FI, MVT::i64));
     else
       return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
                                    CurDAG->getTargetFrameIndex(FI, MVT::i64));
   }
 
   case ISD::ConstantPool: { // TODO: nuke the constant pool
-			    //       (ia64 doesn't need one)
+    // (ia64 doesn't need one)
     ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
     Constant *C = CP->getConstVal();
     SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
@@ -437,18 +438,24 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
-    SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, 
-	                          CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
+    SDOperand Tmp =
+      SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, 
+                                      CurDAG->getRegister(IA64::r1,
+                                                          MVT::i64), GA), 0);
     return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
   }
   
-/* XXX  case ISD::ExternalSymbol: {
-    SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
-	  MVT::i64);
-    SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64, 
-	                          CurDAG->getRegister(IA64::r1, MVT::i64), EA);
-    return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
- }
+/* XXX
+   case ISD::ExternalSymbol: {
+     SDOperand EA = CurDAG->getTargetExternalSymbol(
+       cast<ExternalSymbolSDNode>(N)->getSymbol(),
+       MVT::i64);
+     SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64, 
+                                           CurDAG->getRegister(IA64::r1,
+                                                               MVT::i64),
+                                           EA);
+     return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
+   }
 */
 
   case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
@@ -504,15 +511,16 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
       default: assert(0 && "unknown type in store");
       case MVT::i1: { // this is a bool
         Opc = IA64::ST1; // we store either 0 or 1 as a byte 
-	// first load zero!
-	SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
-	Chain = Initial.getValue(1);
-	// then load 1 into the same reg iff the predicate to store is 1
+        // first load zero!
+        SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
+        Chain = Initial.getValue(1);
+        // then load 1 into the same reg iff the predicate to store is 1
         SDOperand Tmp = ST->getValue();
         AddToISelQueue(Tmp);
-        Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
-                                              CurDAG->getTargetConstant(1, MVT::i64),
-                                              Tmp), 0);
+        Tmp =
+          SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
+                                          CurDAG->getTargetConstant(1, MVT::i64),
+                                          Tmp), 0);
         return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
       }
       case MVT::i64: Opc = IA64::ST8;  break;
@@ -551,14 +559,14 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
   case ISD::CALLSEQ_END: {
     int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
     unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
-                       IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
+      IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
     SDOperand N0 = N->getOperand(0);
     AddToISelQueue(N0);
     return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
   }
 
   case ISD::BR:
-		 // FIXME: we don't need long branches all the time!
+    // FIXME: we don't need long branches all the time!
     SDOperand N0 = N->getOperand(0);
     AddToISelQueue(N0);
     return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, 
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 4bd7cba4b3..55c51d6bbe 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -366,9 +366,9 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
           ValToStore = Val;
         } else {
           RegValuesToPass.push_back(Val);
-	  if(1 /* TODO: if(calling external or varadic function)*/ ) {
-	    ValToConvert = Val; // additionally pass this FP value as an int
-	  }
+          if(1 /* TODO: if(calling external or varadic function)*/ ) {
+            ValToConvert = Val; // additionally pass this FP value as an int
+          }
         }
         break;
       }
@@ -384,7 +384,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
       }
 
       if(ValToConvert.Val) {
-	Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert)); 
+        Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert)); 
       }
     }
 
@@ -492,7 +492,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
       Chain = boolInR8.getValue(1);
       SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
       InFlag = zeroReg.getValue(2);
-      Chain = zeroReg.getValue(1); 	
+      Chain = zeroReg.getValue(1);
       
       RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
       break;
diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp
index 610ab03365..55eb03c7d0 100644
--- a/lib/Target/MSIL/MSILWriter.cpp
+++ b/lib/Target/MSIL/MSILWriter.cpp
@@ -1,6 +1,6 @@
 //===-- MSILWriter.cpp - Library for converting LLVM code to MSIL ---------===//
 //
-//		       The LLVM Compiler Infrastructure
+//                     The LLVM Compiler Infrastructure
 //
 // This file was developed by Roman Samoilov and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
@@ -1333,7 +1333,7 @@ void MSILWriter::printExternals() {
 }
 
 //===----------------------------------------------------------------------===//
-//			 External Interface declaration
+//                      External Interface declaration
 //===----------------------------------------------------------------------===//
 
 bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, std::ostream &o,
diff --git a/lib/Target/MSIL/MSILWriter.h b/lib/Target/MSIL/MSILWriter.h
index c02c856342..7fa039e3d9 100644
--- a/lib/Target/MSIL/MSILWriter.h
+++ b/lib/Target/MSIL/MSILWriter.h
@@ -1,6 +1,6 @@
 //===-- MSILWriter.h - TargetMachine for the MSIL ---------------*- C++ -*-===//
 //
-//		       The LLVM Compiler Infrastructure
+//                     The LLVM Compiler Infrastructure
 //
 // This file was developed by Roman Samoilov and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index a791e2a04a..7371aada07 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -487,13 +487,13 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
     for (unsigned e = NumOps; i != e; ++i) {
       const MachineOperand& MO = MI.getOperand(i);
       if (MO.isRegister()) {
-	unsigned Reg = MO.getReg();
-	// Trunc to byte are actually movb. The real source operand is the low
-	// byte of the register.
-	if (isTrunc8 && i == 1)
-	  Reg = getX86SubSuperRegister(Reg, MVT::i8);
-	if (isX86_64NonExtLowByteReg(Reg))
-	  REX |= 0x40;
+        unsigned Reg = MO.getReg();
+        // Trunc to byte are actually movb. The real source operand is the low
+        // byte of the register.
+        if (isTrunc8 && i == 1)
+          Reg = getX86SubSuperRegister(Reg, MVT::i8);
+        if (isX86_64NonExtLowByteReg(Reg))
+          REX |= 0x40;
       }
     }
 
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index dbdc13207f..664c7e0638 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1345,8 +1345,8 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
     // We should use extra load for direct calls to dllimported functions in
     // non-JIT mode.
     if (getTargetMachine().getCodeModel() != CodeModel::Large
-	&& !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
-					   getTargetMachine(), true))
+        && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
+                                           getTargetMachine(), true))
       Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
   } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
     if (getTargetMachine().getCodeModel() != CodeModel::Large)
diff --git a/lib/Transforms/IPO/IndMemRemoval.cpp b/lib/Transforms/IPO/IndMemRemoval.cpp
index 6c80aca148..eeddad71a9 100644
--- a/lib/Transforms/IPO/IndMemRemoval.cpp
+++ b/lib/Transforms/IPO/IndMemRemoval.cpp
@@ -49,8 +49,8 @@ bool IndMemRemPass::runOnModule(Module &M) {
     assert(F->isDeclaration() && "free not external?");
     if (!F->use_empty()) {
       Function* FN = new Function(F->getFunctionType(), 
-				  GlobalValue::LinkOnceLinkage, 
-				  "free_llvm_bounce", &M);
+                                  GlobalValue::LinkOnceLinkage, 
+                                  "free_llvm_bounce", &M);
       BasicBlock* bb = new BasicBlock("entry",FN);
       Instruction* R = new ReturnInst(bb);
       new FreeInst(FN->arg_begin(), R);
@@ -64,8 +64,8 @@ bool IndMemRemPass::runOnModule(Module &M) {
     assert(F->isDeclaration() && "malloc not external?");
     if (!F->use_empty()) {
       Function* FN = new Function(F->getFunctionType(), 
-				  GlobalValue::LinkOnceLinkage, 
-				  "malloc_llvm_bounce", &M);
+                                  GlobalValue::LinkOnceLinkage, 
+                                  "malloc_llvm_bounce", &M);
       BasicBlock* bb = new BasicBlock("entry",FN);
       Instruction* c = CastInst::createIntegerCast(
           FN->arg_begin(), Type::Int32Ty, false, "c", bb);
diff --git a/lib/Transforms/IPO/Internalize.cpp b/lib/Transforms/IPO/Internalize.cpp
index a1ebe956e5..46d80e592f 100644
--- a/lib/Transforms/IPO/Internalize.cpp
+++ b/lib/Transforms/IPO/Internalize.cpp
@@ -68,7 +68,7 @@ InternalizePass::InternalizePass(bool InternalizeEverything)
 InternalizePass::InternalizePass(const std::vector<const char *>&exportList) 
   : DontInternalize(false){
   for(std::vector<const char *>::const_iterator itr = exportList.begin();
-	itr != exportList.end(); itr++) {
+        itr != exportList.end(); itr++) {
     ExternalNames.insert(*itr);
   }
 }
diff --git a/lib/Transforms/Instrumentation/RSProfiling.cpp b/lib/Transforms/Instrumentation/RSProfiling.cpp
index 2b3adb27cd..7e34786edf 100644
--- a/lib/Transforms/Instrumentation/RSProfiling.cpp
+++ b/lib/Transforms/Instrumentation/RSProfiling.cpp
@@ -60,7 +60,7 @@ namespace {
       cl::values(
                  clEnumValN(GBV, "global", "global counter"),
                  clEnumValN(GBVO, "ra_global", 
-			    "register allocated global counter"),
+                            "register allocated global counter"),
                  clEnumValN(HOSTCC, "rdcc", "cycle counter"),
                  clEnumValEnd));
   
@@ -82,7 +82,7 @@ namespace {
 
   static RegisterAnalysisGroup<RSProfilers> A("Profiling passes");
   static RegisterPass<NullProfilerRS> NP("insert-null-profiling-rs",
-					"Measure profiling framework overhead");
+                                         "Measure profiling framework overhead");
   static RegisterAnalysisGroup<RSProfilers, true> NPT(NP);
 
   /// Chooser - Something that chooses when to make a sample of the profiled code
@@ -155,7 +155,7 @@ namespace {
   };
 
   RegisterPass<ProfilerRS> X("insert-rs-profiling-framework",
-			   "Insert random sampling instrumentation framework");
+                             "Insert random sampling instrumentation framework");
 }
 
 //Local utilities
@@ -202,14 +202,14 @@ void GlobalRandomCounter::ProcessChoicePoint(BasicBlock* bb) {
                              "countercc", t);
 
   Value* nv = BinaryOperator::createSub(l, ConstantInt::get(T, 1),
-                                     "counternew", t);
+                                        "counternew", t);
   new StoreInst(nv, Counter, t);
   t->setCondition(s);
   
   //reset counter
   BasicBlock* oldnext = t->getSuccessor(0);
   BasicBlock* resetblock = new BasicBlock("reset", oldnext->getParent(), 
-					  oldnext);
+                                          oldnext);
   TerminatorInst* t2 = new BranchInst(oldnext, resetblock);
   t->setSuccessor(0, resetblock);
   new StoreInst(ResetValue, Counter, t2);
@@ -275,14 +275,14 @@ void GlobalRandomCounterOpt::ProcessChoicePoint(BasicBlock* bb) {
                              "countercc", t);
 
   Value* nv = BinaryOperator::createSub(l, ConstantInt::get(T, 1),
-                                     "counternew", t);
+                                        "counternew", t);
   new StoreInst(nv, AI, t);
   t->setCondition(s);
   
   //reset counter
   BasicBlock* oldnext = t->getSuccessor(0);
   BasicBlock* resetblock = new BasicBlock("reset", oldnext->getParent(), 
-					  oldnext);
+                                          oldnext);
   TerminatorInst* t2 = new BranchInst(oldnext, resetblock);
   t->setSuccessor(0, resetblock);
   new StoreInst(ResetValue, AI, t2);
@@ -304,7 +304,7 @@ void CycleCounter::ProcessChoicePoint(BasicBlock* bb) {
   CallInst* c = new CallInst(F, "rdcc", t);
   BinaryOperator* b = 
     BinaryOperator::createAnd(c, ConstantInt::get(Type::Int64Ty, rm),
-			      "mrdcc", t);
+                              "mrdcc", t);
   
   ICmpInst *s = new ICmpInst(ICmpInst::ICMP_EQ, b,
                              ConstantInt::get(Type::Int64Ty, 0), 
@@ -342,8 +342,8 @@ void RSProfilers_std::IncrementCounterInBlock(BasicBlock *BB, unsigned CounterNu
   Value *OldVal = new LoadInst(ElementPtr, "OldCounter", InsertPos);
   profcode.insert(OldVal);
   Value *NewVal = BinaryOperator::createAdd(OldVal,
-					    ConstantInt::get(Type::Int32Ty, 1),
-					    "NewCounter", InsertPos);
+                                            ConstantInt::get(Type::Int32Ty, 1),
+                                            "NewCounter", InsertPos);
   profcode.insert(NewVal);
   profcode.insert(new StoreInst(NewVal, ElementPtr, InsertPos));
 }
@@ -366,7 +366,7 @@ Value* ProfilerRS::Translate(Value* v) {
       TransCache[bb] = bb; //don't translate entry block
     else
       TransCache[bb] = new BasicBlock("dup_" + bb->getName(), bb->getParent(), 
-				      NULL);
+                                      NULL);
     return TransCache[bb];
   } else if (Instruction* i = dyn_cast<Instruction>(v)) {
     //we have already translated this
@@ -462,7 +462,7 @@ void ProfilerRS::ProcessBackEdge(BasicBlock* src, BasicBlock* dst, Function& F)
   //b:
   new BranchInst(cast<BasicBlock>(Translate(dst)), bbC);
   new BranchInst(dst, cast<BasicBlock>(Translate(dst)), 
-		 ConstantInt::get(Type::Int1Ty, true), bbCp);
+                 ConstantInt::get(Type::Int1Ty, true), bbCp);
   //c:
   {
     TerminatorInst* iB = src->getTerminator();
@@ -484,7 +484,7 @@ void ProfilerRS::ProcessBackEdge(BasicBlock* src, BasicBlock* dst, Function& F)
   CollapsePhi(dst, bbC);
   //f:
   ReplacePhiPred(cast<BasicBlock>(Translate(dst)),
-		 cast<BasicBlock>(Translate(src)),bbCp);
+                 cast<BasicBlock>(Translate(src)),bbCp);
   CollapsePhi(cast<BasicBlock>(Translate(dst)), bbCp);
   //g:
   for(BasicBlock::iterator ib = dst->begin(), ie = dst->end(); ib != ie;
@@ -494,7 +494,7 @@ void ProfilerRS::ProcessBackEdge(BasicBlock* src, BasicBlock* dst, Function& F)
         if(bbC == phi->getIncomingBlock(x)) {
           phi->addIncoming(Translate(phi->getIncomingValue(x)), bbCp);
           cast<PHINode>(Translate(phi))->addIncoming(phi->getIncomingValue(x), 
-						     bbC);
+                                                     bbC);
         }
       phi->removeIncomingValue(bbC);
     }
@@ -510,15 +510,16 @@ bool ProfilerRS::runOnFunction(Function& F) {
     //assume that stuff worked.  now connect the duplicated basic blocks 
     //with the originals in such a way as to preserve ssa.  yuk!
     for (std::set<std::pair<BasicBlock*, BasicBlock*> >::iterator 
-	   ib = BackEdges.begin(), ie = BackEdges.end(); ib != ie; ++ib)
+           ib = BackEdges.begin(), ie = BackEdges.end(); ib != ie; ++ib)
       ProcessBackEdge(ib->first, ib->second, F);
     
     //oh, and add the edge from the reg2mem created entry node to the 
     //duplicated second node
     TerminatorInst* T = F.getEntryBlock().getTerminator();
     ReplaceInstWithInst(T, new BranchInst(T->getSuccessor(0),
-			       cast<BasicBlock>(Translate(T->getSuccessor(0))),
-					 ConstantInt::get(Type::Int1Ty, true)));
+                                          cast<BasicBlock>(
+                                            Translate(T->getSuccessor(0))),
+                                          ConstantInt::get(Type::Int1Ty, true)));
     
     //do whatever is needed now that the function is duplicated
     c->PrepFunction(&F);
@@ -527,7 +528,7 @@ bool ProfilerRS::runOnFunction(Function& F) {
     ChoicePoints.insert(&F.getEntryBlock());
     
     for (std::set<BasicBlock*>::iterator 
-	   ii = ChoicePoints.begin(), ie = ChoicePoints.end(); ii != ie; ++ii)
+           ii = ChoicePoints.begin(), ie = ChoicePoints.end(); ii != ie; ++ii)
       c->ProcessChoicePoint(*ii);
     
     ChoicePoints.clear();
diff --git a/lib/Transforms/Scalar/LowerPacked.cpp b/lib/Transforms/Scalar/LowerPacked.cpp
index 4e1d280b1e..10a5e60a86 100644
--- a/lib/Transforms/Scalar/LowerPacked.cpp
+++ b/lib/Transforms/Scalar/LowerPacked.cpp
@@ -379,7 +379,7 @@ void LowerPacked::visitExtractElementInst(ExtractElementInst& EI)
       new AllocaInst(PTy->getElementType(),
                      ConstantInt::get(Type::Int32Ty, PTy->getNumElements()),
                      EI.getName() + ".alloca", 
-		     EI.getParent()->getParent()->getEntryBlock().begin());
+                     EI.getParent()->getParent()->getEntryBlock().begin());
     for (unsigned i = 0; i < PTy->getNumElements(); ++i) {
       GetElementPtrInst *GEP = 
         new GetElementPtrInst(alloca, ConstantInt::get(Type::Int32Ty, i),
diff --git a/lib/Transforms/Scalar/Reg2Mem.cpp b/lib/Transforms/Scalar/Reg2Mem.cpp
index e1eab65bd4..e013cedb0d 100644
--- a/lib/Transforms/Scalar/Reg2Mem.cpp
+++ b/lib/Transforms/Scalar/Reg2Mem.cpp
@@ -44,7 +44,7 @@ namespace {
       for(Value::use_iterator ii = i->use_begin(), ie = i->use_end();
           ii != ie; ++ii)
         if (cast<Instruction>(*ii)->getParent() != bb ||
-	    isa<PHINode>(*ii))
+            isa<PHINode>(*ii))
           return true;
       return false;
     }
@@ -52,9 +52,9 @@ namespace {
     virtual bool runOnFunction(Function &F) {
       if (!F.isDeclaration()) {
         //give us a clean block
-	BasicBlock* bbold = &F.getEntryBlock();
-	BasicBlock* bbnew = new BasicBlock("allocablock", &F, &F.getEntryBlock());
-	new BranchInst(bbold, bbnew);
+        BasicBlock* bbold = &F.getEntryBlock();
+        BasicBlock* bbnew = new BasicBlock("allocablock", &F, &F.getEntryBlock());
+        new BranchInst(bbold, bbnew);
 
         //find the instructions
         std::list<Instruction*> worklist;
diff --git a/lib/Transforms/Utils/CodeExtractor.cpp b/lib/Transforms/Utils/CodeExtractor.cpp
index 6ad7c2a899..656e6dcc00 100644
--- a/lib/Transforms/Utils/CodeExtractor.cpp
+++ b/lib/Transforms/Utils/CodeExtractor.cpp
@@ -151,7 +151,7 @@ void CodeExtractor::severSplitPHINodes(BasicBlock *&Header) {
     for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I)
       if (DT->getNode(I)->getIDom()->getBlock() == OldPred) {
         DT->changeImmediateDominator(DT->getNode(I), DT->getNode(NewBB));
-	EF->setImmediateDominator(I, NewBB);
+        EF->setImmediateDominator(I, NewBB);
       }
   }
 
diff --git a/lib/Transforms/Utils/LowerAllocations.cpp b/lib/Transforms/Utils/LowerAllocations.cpp
index 8acaeed26b..cb2f88558e 100644
--- a/lib/Transforms/Utils/LowerAllocations.cpp
+++ b/lib/Transforms/Utils/LowerAllocations.cpp
@@ -43,7 +43,7 @@ namespace {
       AU.addRequired<TargetData>();
       AU.setPreservesCFG();
 
-      // This is a cluster of orthogonal Transforms:	
+      // This is a cluster of orthogonal Transforms:
       AU.addPreserved<UnifyFunctionExitNodes>();
       AU.addPreservedID(PromoteMemoryToRegisterID);
       AU.addPreservedID(LowerSelectID);
diff --git a/lib/Transforms/Utils/LowerInvoke.cpp b/lib/Transforms/Utils/LowerInvoke.cpp
index e1712bce43..a1bd065df8 100644
--- a/lib/Transforms/Utils/LowerInvoke.cpp
+++ b/lib/Transforms/Utils/LowerInvoke.cpp
@@ -80,7 +80,7 @@ namespace {
     bool runOnFunction(Function &F);
  
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-      // This is a cluster of orthogonal Transforms	
+      // This is a cluster of orthogonal Transforms
       AU.addPreservedID(PromoteMemoryToRegisterID);
       AU.addPreservedID(LowerSelectID);
       AU.addPreservedID(LowerSwitchID);
diff --git a/lib/Transforms/Utils/LowerSelect.cpp b/lib/Transforms/Utils/LowerSelect.cpp
index 27e1866eaf..120c3b19c7 100644
--- a/lib/Transforms/Utils/LowerSelect.cpp
+++ b/lib/Transforms/Utils/LowerSelect.cpp
@@ -37,7 +37,7 @@ namespace {
 
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
       // This certainly destroys the CFG.
-      // This is a cluster of orthogonal Transforms:	
+      // This is a cluster of orthogonal Transforms:
       AU.addPreserved<UnifyFunctionExitNodes>();
       AU.addPreservedID(PromoteMemoryToRegisterID);
       AU.addPreservedID(LowerSwitchID);
diff --git a/lib/Transforms/Utils/LowerSwitch.cpp b/lib/Transforms/Utils/LowerSwitch.cpp
index 9e85974070..4a2dd9a9e0 100644
--- a/lib/Transforms/Utils/LowerSwitch.cpp
+++ b/lib/Transforms/Utils/LowerSwitch.cpp
@@ -33,7 +33,7 @@ namespace {
     virtual bool runOnFunction(Function &F);
     
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-      // This is a cluster of orthogonal Transforms	
+      // This is a cluster of orthogonal Transforms
       AU.addPreserved<UnifyFunctionExitNodes>();
       AU.addPreservedID(PromoteMemoryToRegisterID);
       AU.addPreservedID(LowerSelectID);
diff --git a/lib/Transforms/Utils/Mem2Reg.cpp b/lib/Transforms/Utils/Mem2Reg.cpp
index 78117fb11e..6e2bcb08fe 100644
--- a/lib/Transforms/Utils/Mem2Reg.cpp
+++ b/lib/Transforms/Utils/Mem2Reg.cpp
@@ -40,7 +40,7 @@ namespace {
       AU.addRequired<DominanceFrontier>();
       AU.addRequired<TargetData>();
       AU.setPreservesCFG();
-      // This is a cluster of orthogonal Transforms	
+      // This is a cluster of orthogonal Transforms
       AU.addPreserved<UnifyFunctionExitNodes>();
       AU.addPreservedID(LowerSelectID);
       AU.addPreservedID(LowerSwitchID);
diff --git a/lib/VMCore/PassManager.cpp b/lib/VMCore/PassManager.cpp
index cdeb256472..37b8a5fbf3 100644
--- a/lib/VMCore/PassManager.cpp
+++ b/lib/VMCore/PassManager.cpp
@@ -1293,7 +1293,7 @@ void PMStack::dump() {
 /// Find appropriate Module Pass Manager in the PM Stack and
 /// add self into that manager. 
 void ModulePass::assignPassManager(PMStack &PMS, 
-				   PassManagerType PreferredType) {
+                                   PassManagerType PreferredType) {
 
   // Find Module Pass Manager
   while(!PMS.empty()) {
@@ -1312,7 +1312,7 @@ void ModulePass::assignPassManager(PMStack &PMS,
 /// Find appropriate Function Pass Manager or Call Graph Pass Manager
 /// in the PM Stack and add self into that manager. 
 void FunctionPass::assignPassManager(PMStack &PMS,
-				     PassManagerType PreferredType) {
+                                     PassManagerType PreferredType) {
 
   // Find Module Pass Manager (TODO : Or Call Graph Pass Manager)
   while(!PMS.empty()) {
@@ -1357,7 +1357,7 @@ void FunctionPass::assignPassManager(PMStack &PMS,
 /// Find appropriate Basic Pass Manager or Call Graph Pass Manager
 /// in the PM Stack and add self into that manager. 
 void BasicBlockPass::assignPassManager(PMStack &PMS,
-				       PassManagerType PreferredType) {
+                                       PassManagerType PreferredType) {
 
   BBPassManager *BBP = NULL;