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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-19 16:37:00 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-19 16:37:00 +0000 |
| commit | c7c7e1502a62123a5e54fe6ff7da490bf26d319e (patch) | |
| tree | f1c7abae22d4ce68dc1d2367d16bcd84c956d5f7 /lib | |
| parent | 6fec715a1a662ce3b560f85c710875cfeeb1fb98 (diff) | |
| download | llvm-c7c7e1502a62123a5e54fe6ff7da490bf26d319e.tar.gz llvm-c7c7e1502a62123a5e54fe6ff7da490bf26d319e.tar.bz2 llvm-c7c7e1502a62123a5e54fe6ff7da490bf26d319e.tar.xz | |
[SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186689 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 5ffb86b32e..56b7a1f63b 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -564,11 +564,17 @@ defm : SXB<add, GR64, AGFR>; let Defs = [CC] in { // Addition of a register. let isCommutable = 1 in { - def ALR : BinaryRR <"al", 0x1E, addc, GR32, GR32>; - def ALGR : BinaryRRE<"alg", 0xB90A, addc, GR64, GR64>; + defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>; + defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>; } def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>; + // Addition of signed 16-bit immediates. + def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, + Requires<[FeatureDistinctOps]>; + def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, + Requires<[FeatureDistinctOps]>; + // Addition of unsigned 32-bit immediates. def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; @@ -614,9 +620,9 @@ defm : SXB<sub, GR64, SGFR>; // Subtraction producing a carry. let Defs = [CC] in { // Subtraction of a register. - def SLR : BinaryRR <"sl", 0x1F, subc, GR32, GR32>; + defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>; def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>; - def SLGR : BinaryRRE<"slg", 0xB90B, subc, GR64, GR64>; + defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>; // Subtraction of unsigned 32-bit immediates. These don't match // subc because we prefer addc for constants. |