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| author | Eli Friedman <eli.friedman@gmail.com> | 2009-08-22 03:13:10 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2009-08-22 03:13:10 +0000 |
| commit | ce392eb3ea16b781de89b7ff8f42c39f8b3df30e (patch) | |
| tree | e221dde4f89d2ff0a80a8c4c9f0967550c59c791 /lib | |
| parent | b8b85cfd4d7b8e54e3323e555c3e644b3af46ccb (diff) | |
| download | llvm-ce392eb3ea16b781de89b7ff8f42c39f8b3df30e.tar.gz llvm-ce392eb3ea16b781de89b7ff8f42c39f8b3df30e.tar.bz2 llvm-ce392eb3ea16b781de89b7ff8f42c39f8b3df30e.tar.xz | |
Make x86 test actually test x86 code generation. Fix the
construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f04b45dc79..7d8362c93d 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2134,8 +2134,11 @@ static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, N->getOperand(0), NegatedCount); } - assert(VT == MVT::i64 && - (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && + // We can get here for a node like i32 = ISD::SHL i32, i64 + if (VT != MVT::i64) + return SDValue(); + + assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!"); // We only lower SRA, SRL of 1 here, all others use generic lowering. |