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| author | Tim Northover <tnorthover@apple.com> | 2014-04-02 14:38:58 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-02 14:38:58 +0000 |
| commit | 3844cadc9aac3cef059434f2f34024c6cf6573de (patch) | |
| tree | 0cce2f5bc5f9e540f88ba1858bc9c6f788641317 /test/CodeGen/ARM64 | |
| parent | 87e824120d1cbcca2a98449198060fde5493e47d (diff) | |
| download | llvm-3844cadc9aac3cef059434f2f34024c6cf6573de.tar.gz llvm-3844cadc9aac3cef059434f2f34024c6cf6573de.tar.bz2 llvm-3844cadc9aac3cef059434f2f34024c6cf6573de.tar.xz | |
ARM64: make sure first argument to INSERT_SUBVECTOR has right type.
Again, coalescing and other optimisations swiftly made the MachineInstrs
consistent again, but when compiled at -O0 a bad INSERT_SUBREGISTER was
produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205423 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM64')
| -rw-r--r-- | test/CodeGen/ARM64/simd-scalar-to-vector.ll | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/test/CodeGen/ARM64/simd-scalar-to-vector.ll b/test/CodeGen/ARM64/simd-scalar-to-vector.ll index fe0c6feddd..6c0b840a5c 100644 --- a/test/CodeGen/ARM64/simd-scalar-to-vector.ll +++ b/test/CodeGen/ARM64/simd-scalar-to-vector.ll @@ -1,10 +1,15 @@ ; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s +; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -O0 | FileCheck %s --check-prefix=CHECK-FAST define <16 x i8> @foo(<16 x i8> %a) nounwind optsize readnone ssp { -; CHECK: uaddlv.16b h0, v0 -; CHECK: rshrn.8b v0, v0, #4 -; CHECK: dup.16b v0, v0[0] +; CHECK: uaddlv.16b h0, v0 +; CHECK: rshrn.8b v0, v0, #4 +; CHECK: dup.16b v0, v0[0] ; CHECK: ret + +; CHECK-FAST: uaddlv.16b +; CHECK-FAST: rshrn.8b +; CHECK-FAST: dup.16b %tmp = tail call i32 @llvm.arm64.neon.uaddlv.i32.v16i8(<16 x i8> %a) nounwind %tmp1 = trunc i32 %tmp to i16 %tmp2 = insertelement <8 x i16> undef, i16 %tmp1, i32 0 |