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| author | Louis Gerbarg <lgg@apple.com> | 2014-04-11 22:27:58 +0000 |
|---|---|---|
| committer | Louis Gerbarg <lgg@apple.com> | 2014-04-11 22:27:58 +0000 |
| commit | 5672630b7c8215ee5b54ea754beb42c18c132c05 (patch) | |
| tree | fc3862cfe434511c794399dd1a42e81f7db8d9dc /test/CodeGen/ARM64 | |
| parent | 0f6d8c6c8dcb0401eb34adf6806a13add6243918 (diff) | |
| download | llvm-5672630b7c8215ee5b54ea754beb42c18c132c05.tar.gz llvm-5672630b7c8215ee5b54ea754beb42c18c132c05.tar.bz2 llvm-5672630b7c8215ee5b54ea754beb42c18c132c05.tar.xz | |
Add ARM64 CLS patterns
This patch adds patterns to generate the cls instruction ARM64. Includes tests
for 64 bit and 32 bit operands.
rdar://15611957
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206079 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM64')
| -rw-r--r-- | test/CodeGen/ARM64/clrsb.ll | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/test/CodeGen/ARM64/clrsb.ll b/test/CodeGen/ARM64/clrsb.ll new file mode 100644 index 0000000000..042e52e5e7 --- /dev/null +++ b/test/CodeGen/ARM64/clrsb.ll @@ -0,0 +1,36 @@ +; RUN: llc < %s -march=arm64 | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-ios7.0.0" + +; Function Attrs: nounwind readnone +declare i32 @llvm.ctlz.i32(i32, i1) #0 +declare i64 @llvm.ctlz.i64(i64, i1) #1 + +; Function Attrs: nounwind ssp +define i32 @clrsb32(i32 %x) #2 { +entry: + %shr = ashr i32 %x, 31 + %xor = xor i32 %shr, %x + %mul = shl i32 %xor, 1 + %add = or i32 %mul, 1 + %0 = tail call i32 @llvm.ctlz.i32(i32 %add, i1 false) + + ret i32 %0 +; CHECK-LABEL: clrsb32 +; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]] +} + +; Function Attrs: nounwind ssp +define i64 @clrsb64(i64 %x) #3 { +entry: + %shr = ashr i64 %x, 63 + %xor = xor i64 %shr, %x + %mul = shl nsw i64 %xor, 1 + %add = or i64 %mul, 1 + %0 = tail call i64 @llvm.ctlz.i64(i64 %add, i1 false) + + ret i64 %0 +; CHECK-LABEL: clrsb64 +; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]] +} |