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authorTim Northover <tnorthover@apple.com>2014-04-04 14:49:30 +0000
committerTim Northover <tnorthover@apple.com>2014-04-04 14:49:30 +0000
commit659e09e3729b903ee299300e4d29a482ce986bab (patch)
tree9e7df90d53353b6a30255931ba24330a12afc4fa /test/CodeGen/ARM64
parent4a4d62bfb923f81d0cc8203bdca487a764bb0945 (diff)
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DAGLegalize: add last-ditch type-legalization for VSELECT.
When LLVM sees something like (v1iN (vselect v1i1, v1iN, v1iN)) it can decide that the result is OK (v1i64 is legal on AArch64, for example) but it still need scalarising because of that v1i1. There was no code to do this though. AArch64 and ARM64 have DAG combines to produce efficient code and prevent that occuring in *most* such situations, but there are edge cases that they miss. This adds a legalization to cope with that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205626 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM64')
-rw-r--r--test/CodeGen/ARM64/neon-v1i1-setcc.ll9
1 files changed, 9 insertions, 0 deletions
diff --git a/test/CodeGen/ARM64/neon-v1i1-setcc.ll b/test/CodeGen/ARM64/neon-v1i1-setcc.ll
index a7e59fbc00..d7a0771f7b 100644
--- a/test/CodeGen/ARM64/neon-v1i1-setcc.ll
+++ b/test/CodeGen/ARM64/neon-v1i1-setcc.ll
@@ -50,6 +50,15 @@ define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x doubl
ret <1 x double> %res
}
+define <1 x i64> @test_select_v1i1_3(i64 %lhs, i64 %rhs, <1 x i64> %v3) {
+; CHECK-LABEL: test_select_v1i1_3:
+; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
+ %tst = icmp eq i64 %lhs, %rhs
+ %evil = insertelement <1 x i1> undef, i1 %tst, i32 0
+ %res = select <1 x i1> %evil, <1 x i64> zeroinitializer, <1 x i64> %v3
+ ret <1 x i64> %res
+}
+
define i32 @test_br_extr_cmp(<1 x i64> %v1, <1 x i64> %v2) {
; CHECK-LABEL: test_br_extr_cmp:
; CHECK: cmp x{{[0-9]+}}, x{{[0-9]+}}