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author | Tim Northover <tnorthover@apple.com> | 2014-04-16 09:03:09 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-04-16 09:03:09 +0000 |
commit | 7474c171e1185812655352e32d2a44339aab0250 (patch) | |
tree | 531a65e3c63b04c3365c698e55fa5caa6d784384 /test/CodeGen/ARM64 | |
parent | 8b3d82accc5b97919945c19f6c91f382888a8b29 (diff) | |
download | llvm-7474c171e1185812655352e32d2a44339aab0250.tar.gz llvm-7474c171e1185812655352e32d2a44339aab0250.tar.bz2 llvm-7474c171e1185812655352e32d2a44339aab0250.tar.xz |
DAGCombiner: don't optimise non-existant litpool load
This particular DAG combine is designed to kick in when both ConstantFPs will
end up being loaded via a litpool, however those nodes have a semi-legal
status, dictated by isFPImmLegal so in some cases there wouldn't have been a
litpool in the first place. Don't try to be clever in those circumstances.
Picked up while merging some AArch64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206365 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM64')
-rw-r--r-- | test/CodeGen/ARM64/fcmp-opt.ll | 103 |
1 files changed, 67 insertions, 36 deletions
diff --git a/test/CodeGen/ARM64/fcmp-opt.ll b/test/CodeGen/ARM64/fcmp-opt.ll index 17412dde74..a90dabb4a4 100644 --- a/test/CodeGen/ARM64/fcmp-opt.ll +++ b/test/CodeGen/ARM64/fcmp-opt.ll @@ -3,7 +3,7 @@ define i1 @fcmp_float1(float %a) nounwind ssp { entry: -; CHECK: @fcmp_float1 +; CHECK-LABEL: @fcmp_float1 ; CHECK: fcmp s0, #0.0 ; CHECK: csinc w0, wzr, wzr, eq %cmp = fcmp une float %a, 0.000000e+00 @@ -12,7 +12,7 @@ entry: define i1 @fcmp_float2(float %a, float %b) nounwind ssp { entry: -; CHECK: @fcmp_float2 +; CHECK-LABEL: @fcmp_float2 ; CHECK: fcmp s0, s1 ; CHECK: csinc w0, wzr, wzr, eq %cmp = fcmp une float %a, %b @@ -21,7 +21,7 @@ entry: define i1 @fcmp_double1(double %a) nounwind ssp { entry: -; CHECK: @fcmp_double1 +; CHECK-LABEL: @fcmp_double1 ; CHECK: fcmp d0, #0.0 ; CHECK: csinc w0, wzr, wzr, eq %cmp = fcmp une double %a, 0.000000e+00 @@ -30,7 +30,7 @@ entry: define i1 @fcmp_double2(double %a, double %b) nounwind ssp { entry: -; CHECK: @fcmp_double2 +; CHECK-LABEL: @fcmp_double2 ; CHECK: fcmp d0, d1 ; CHECK: csinc w0, wzr, wzr, eq %cmp = fcmp une double %a, %b @@ -39,108 +39,137 @@ entry: ; Check each fcmp condition define float @fcmp_oeq(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_oeq +; CHECK-LABEL: @fcmp_oeq ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ne +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], eq + %cmp = fcmp oeq float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_ogt(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_ogt +; CHECK-LABEL: @fcmp_ogt ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, le +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], gt + %cmp = fcmp ogt float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_oge(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_oge +; CHECK-LABEL: @fcmp_oge ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, lt +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ge + %cmp = fcmp oge float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_olt(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_olt +; CHECK-LABEL: @fcmp_olt ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, pl +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], mi + %cmp = fcmp olt float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_ole(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_ole +; CHECK-LABEL: @fcmp_ole ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, hi +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ls + %cmp = fcmp ole float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_ord(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_ord +; CHECK-LABEL: @fcmp_ord ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, vs +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vc %cmp = fcmp ord float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_uno(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_uno +; CHECK-LABEL: @fcmp_uno ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, vc +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vs %cmp = fcmp uno float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_ugt(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_ugt +; CHECK-LABEL: @fcmp_ugt ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ls +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], hi %cmp = fcmp ugt float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_uge(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_uge +; CHECK-LABEL: @fcmp_uge ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, mi +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], pl %cmp = fcmp uge float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_ult(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_ult +; CHECK-LABEL: @fcmp_ult ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ge +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], lt %cmp = fcmp ult float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_ule(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_ule +; CHECK-LABEL: @fcmp_ule ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, gt +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], le %cmp = fcmp ule float %a, %b %conv = uitofp i1 %cmp to float ret float %conv } define float @fcmp_une(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_une +; CHECK-LABEL: @fcmp_une ; CHECK: fcmp s0, s1 -; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ne %cmp = fcmp une float %a, %b %conv = uitofp i1 %cmp to float ret float %conv @@ -149,11 +178,12 @@ define float @fcmp_une(float %a, float %b) nounwind ssp { ; Possible opportunity for improvement. See comment in ; ARM64TargetLowering::LowerSETCC() define float @fcmp_one(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_one +; CHECK-LABEL: @fcmp_one ; fcmp s0, s1 -; orr w0, wzr, #0x1 -; csel w1, w0, wzr, mi -; csel w0, w0, wzr, gt +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], mi +; CHECK: fcsel s0, s[[ONE]], [[TMP]], gt %cmp = fcmp one float %a, %b %conv = uitofp i1 %cmp to float ret float %conv @@ -162,11 +192,12 @@ define float @fcmp_one(float %a, float %b) nounwind ssp { ; Possible opportunity for improvement. See comment in ; ARM64TargetLowering::LowerSETCC() define float @fcmp_ueq(float %a, float %b) nounwind ssp { -; CHECK: @fcmp_ueq +; CHECK-LABEL: @fcmp_ueq ; CHECK: fcmp s0, s1 -; orr w0, wzr, #0x1 -; CHECK: csel [[REG1:w[0-9]]], [[REG2:w[0-9]+]], wzr, eq -; CHECK: csel {{w[0-9]+}}, [[REG2]], [[REG1]], vs +; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0 +; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0 +; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], eq +; CHECK: fcsel s0, s[[ONE]], [[TMP]], vs %cmp = fcmp ueq float %a, %b %conv = uitofp i1 %cmp to float ret float %conv |