summaryrefslogtreecommitdiff
path: root/test/CodeGen/PowerPC
diff options
context:
space:
mode:
authorHal Finkel <hfinkel@anl.gov>2014-03-27 21:26:33 +0000
committerHal Finkel <hfinkel@anl.gov>2014-03-27 21:26:33 +0000
commit276d854549f851c7d09c2e6a61bc2ca4e6973f6b (patch)
treeaa9b9f90ae7738fdb58c48eea312554e5bc4bfd8 /test/CodeGen/PowerPC
parentb5e6ddca565a437dcc25b28c756cde00b6901054 (diff)
downloadllvm-276d854549f851c7d09c2e6a61bc2ca4e6973f6b.tar.gz
llvm-276d854549f851c7d09c2e6a61bc2ca4e6973f6b.tar.bz2
llvm-276d854549f851c7d09c2e6a61bc2ca4e6973f6b.tar.xz
[PowerPC] Expand v2i64 shifts
These operations need to be expanded during legalization so that isel does not crash. In theory, we might be able to custom lower some of these. That, however, would need to be follow-up work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204963 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
-rw-r--r--test/CodeGen/PowerPC/vsx.ll42
1 files changed, 42 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll
index 2524251a20..89499560b3 100644
--- a/test/CodeGen/PowerPC/vsx.ll
+++ b/test/CodeGen/PowerPC/vsx.ll
@@ -487,3 +487,45 @@ define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
; CHECK: blr
}
+define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
+ %v = shl <2 x i64> %a, %b
+ ret <2 x i64> %v
+
+; CHECK-LABEL: @test60
+; This should scalarize, and the current code quality is not good.
+; CHECK: stxvd2x
+; CHECK: stxvd2x
+; CHECK: sld
+; CHECK: sld
+; CHECK: lxvd2x
+; CHECK: blr
+}
+
+define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
+ %v = lshr <2 x i64> %a, %b
+ ret <2 x i64> %v
+
+; CHECK-LABEL: @test61
+; This should scalarize, and the current code quality is not good.
+; CHECK: stxvd2x
+; CHECK: stxvd2x
+; CHECK: srd
+; CHECK: srd
+; CHECK: lxvd2x
+; CHECK: blr
+}
+
+define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
+ %v = ashr <2 x i64> %a, %b
+ ret <2 x i64> %v
+
+; CHECK-LABEL: @test62
+; This should scalarize, and the current code quality is not good.
+; CHECK: stxvd2x
+; CHECK: stxvd2x
+; CHECK: srad
+; CHECK: srad
+; CHECK: lxvd2x
+; CHECK: blr
+}
+