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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-12-10 10:49:34 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-12-10 10:49:34 +0000 |
| commit | aedb288d864bf20a708cca580fa87ac848389f79 (patch) | |
| tree | 433a286e31fa441c4784a9d1b95ce1eb49e97032 /test/CodeGen/SystemZ/atomic-store-01.ll | |
| parent | 086791eca2260c03c7bbdd37a53626d16656f0ca (diff) | |
| download | llvm-aedb288d864bf20a708cca580fa87ac848389f79.tar.gz llvm-aedb288d864bf20a708cca580fa87ac848389f79.tar.bz2 llvm-aedb288d864bf20a708cca580fa87ac848389f79.tar.xz | |
Add TargetLowering::prepareVolatileOrAtomicLoad
One unusual feature of the z architecture is that the result of a
previous load can be reused indefinitely for subsequent loads, even if
a cache-coherent store to that location is performed by another CPU.
A special serializing instruction must be used if you want to force
a load to be reattempted.
Since volatile loads are not supposed to be omitted in this way,
we should insert a serializing instruction before each such load.
The same goes for atomic loads.
The patch implements this at the IR->DAG boundary, in a similar way
to atomic fences. It is a no-op for targets other than SystemZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196906 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/atomic-store-01.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/atomic-store-01.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/test/CodeGen/SystemZ/atomic-store-01.ll b/test/CodeGen/SystemZ/atomic-store-01.ll index 53ed24f623..952e1a9121 100644 --- a/test/CodeGen/SystemZ/atomic-store-01.ll +++ b/test/CodeGen/SystemZ/atomic-store-01.ll @@ -2,11 +2,10 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; This is just a placeholder to make sure that stores are handled. -; The CS-based sequence is probably far too conservative. define void @f1(i8 %val, i8 *%src) { ; CHECK-LABEL: f1: -; CHECK: cs +; CHECK: stc %r2, 0(%r3) +; CHECK: bcr 1{{[45]}}, %r0 ; CHECK: br %r14 store atomic i8 %val, i8 *%src seq_cst, align 1 ret void |