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| author | Michael Liao <michael.liao@intel.com> | 2012-09-26 08:22:37 +0000 |
|---|---|---|
| committer | Michael Liao <michael.liao@intel.com> | 2012-09-26 08:22:37 +0000 |
| commit | 0832a72a662043efad72f090023a19156974fc0c (patch) | |
| tree | 142437d65ba83a4d47c0c26434b489674d552f10 /test/CodeGen | |
| parent | c7c42f71aad7d33892de73d6d6397e38814b0e97 (diff) | |
| download | llvm-0832a72a662043efad72f090023a19156974fc0c.tar.gz llvm-0832a72a662043efad72f090023a19156974fc0c.tar.bz2 llvm-0832a72a662043efad72f090023a19156974fc0c.tar.xz | |
Add MULX code generation support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164673 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/X86/mulx32.ll | 22 | ||||
| -rw-r--r-- | test/CodeGen/X86/mulx64.ll | 22 |
2 files changed, 44 insertions, 0 deletions
diff --git a/test/CodeGen/X86/mulx32.ll b/test/CodeGen/X86/mulx32.ll new file mode 100644 index 0000000000..6a6450d500 --- /dev/null +++ b/test/CodeGen/X86/mulx32.ll @@ -0,0 +1,22 @@ +; RUN: llc -mcpu=core-avx2 -march=x86 < %s | FileCheck %s + +define i64 @f1(i32 %a, i32 %b) { + %x = zext i32 %a to i64 + %y = zext i32 %b to i64 + %r = mul i64 %x, %y +; CHECK: f1 +; CHECK: mulxl +; CHECK: ret + ret i64 %r +} + +define i64 @f2(i32 %a, i32* %p) { + %b = load i32* %p + %x = zext i32 %a to i64 + %y = zext i32 %b to i64 + %r = mul i64 %x, %y +; CHECK: f1 +; CHECK: mulxl ({{.+}}), %{{.+}}, %{{.+}} +; CHECK: ret + ret i64 %r +} diff --git a/test/CodeGen/X86/mulx64.ll b/test/CodeGen/X86/mulx64.ll new file mode 100644 index 0000000000..c59adc6069 --- /dev/null +++ b/test/CodeGen/X86/mulx64.ll @@ -0,0 +1,22 @@ +; RUN: llc -mcpu=core-avx2 -march=x86-64 < %s | FileCheck %s + +define i128 @f1(i64 %a, i64 %b) { + %x = zext i64 %a to i128 + %y = zext i64 %b to i128 + %r = mul i128 %x, %y +; CHECK: f1 +; CHECK: mulxq +; CHECK: ret + ret i128 %r +} + +define i128 @f2(i64 %a, i64* %p) { + %b = load i64* %p + %x = zext i64 %a to i128 + %y = zext i64 %b to i128 + %r = mul i128 %x, %y +; CHECK: f1 +; CHECK: mulxq ({{.+}}), %{{.+}}, %{{.+}} +; CHECK: ret + ret i128 %r +} |