summaryrefslogtreecommitdiff
path: root/test/CodeGen
Commit message (Expand)AuthorAge
* [x86] Fix a bug in the v8i16 shuffling exposed by the new splat-likeChandler Carruth2014-06-28
* [x86] Add handling for splat-like widenings of v16i8 shuffles.Chandler Carruth2014-06-28
* This file wasn't supposed to be checked inDavid Majnemer2014-06-28
* Revert "Temporary hack to try cleaning extra .s file from bots."Matt Arsenault2014-06-27
* Temporary hack to try cleaning extra .s file from bots.Matt Arsenault2014-06-27
* [AArch64] Fix memset ICE when memset value is f128.Chad Rosier2014-06-27
* [x86] Fix another bug hit when bootstrapping with the new shuffleChandler Carruth2014-06-27
* [NVPTX] Add reflect intrinsic (better than matching by function name)Justin Holewinski2014-06-27
* [NVPTX] Add 'b' asm constraintJustin Holewinski2014-06-27
* [NVPTX] Error out if initializer is given for variable in an address space th...Justin Holewinski2014-06-27
* [NVPTX] Add support for .managed variables for UVMJustin Holewinski2014-06-27
* [NVPTX] Emit .weak linkage for link_once, weak, available_externally, and com...Justin Holewinski2014-06-27
* [NVPTX] Fix handling of ldg/ldu intrinsics.Justin Holewinski2014-06-27
* [NVPTX] Clean up argument lowering code and properly handle alignment for str...Justin Holewinski2014-06-27
* [NVPTX] Add support for [SHL,SRA,SRL]_PARTSJustin Holewinski2014-06-27
* [NVPTX] Implement fma and imad contraction as target DAGCombiner patternsJustin Holewinski2014-06-27
* [NVPTX] Add support for efficient rotate instructions on SM 3.2+Justin Holewinski2014-06-27
* [NVPTX] Add missing isel patterns for 64-bit atomicsJustin Holewinski2014-06-27
* [NVPTX] Add isel patterns for bit-field extract (bfe)Justin Holewinski2014-06-27
* [NVPTX] Add support for isspacep instructionJustin Holewinski2014-06-27
* [NVPTX] Add support for envreg readsJustin Holewinski2014-06-27
* [NVPTX] Emit .weak when linkage is not external, internal, or privateJustin Holewinski2014-06-27
* [x86] Fix a miscompile in the new shuffle lowering uncovered byChandler Carruth2014-06-27
* IR: Add COMDATs to the IRDavid Majnemer2014-06-27
* Fix test so it doesn't try to write out temporary files into the test tree.David Blaikie2014-06-27
* R600: Don't crash on unhandled instruction in promote allocaMatt Arsenault2014-06-27
* [PowerPC] Constrain base register in PPCRegisterInfo::resolveFrameIndexUlrich Weigand2014-06-27
* [x86] Teach the target combine step to aggressively fold pshufd insturcions.Chandler Carruth2014-06-27
* [x86] Teach the target-specific combining how to aggressively foldChandler Carruth2014-06-27
* [x86] Teach the X86 backend to DAG-combine SSE2 shuffles that areChandler Carruth2014-06-27
* [x86] Begin a significant overhaul of how vector lowering is done in theChandler Carruth2014-06-27
* MachineScheduler: add some book-keeping to fix an assert.Andrew Trick2014-06-27
* R600: Add some testcases for promote alloca pass.Matt Arsenault2014-06-27
* [StackMaps] Enable patchpoint liveness analysis per default.Juergen Ributzka2014-06-26
* [Stackmaps] Remove the liveness calculation for stackmap intrinsics.Juergen Ributzka2014-06-26
* R600/SI: Add FP mode bits to binary.Matt Arsenault2014-06-26
* [X86] Improve the selection of SSE3/AVX addsub instructions. Andrea Di Biagio2014-06-26
* R600: Fix vector FMAMatt Arsenault2014-06-26
* [FastISel][X86] Only fold the cmp into the select when both instructions are ...Juergen Ributzka2014-06-25
* [X86] Always prefer to lower a VECTOR_SHUFFLE into a BLENDI instead of SHUFP ...Andrea Di Biagio2014-06-25
* Rename loop unrolling and loop vectorizer metadata to have a common prefix.Eli Bendersky2014-06-25
* [x86] Add intrinsics for the pshufd, pshuflw, and pshufhw instructions.Chandler Carruth2014-06-25
* Re-apply r211399, "Generate native unwind info on Win64" with a fix to ignore...NAKAMURA Takumi2014-06-25
* [X86] Add target combine rule to select ADDSUB instructions from a build_vectorAndrea Di Biagio2014-06-25
* Fix a regression from r211653.Rafael Espindola2014-06-25
* CodeGen/X86/pr20088.ll: Add -march=x86-64, or llc fails due to non-x86 defaul...NAKAMURA Takumi2014-06-25
* [FastISel][X86] Fold XALU condition into branch and compare.Juergen Ributzka2014-06-24
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-24
* Print a=b as an assignment.Rafael Espindola2014-06-24
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-24