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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-26 10:45:21 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-26 10:45:21 +0000 |
commit | 817812f61caa50ba3ce67ceb5a033cb69a3eea5c (patch) | |
tree | 3246ef4217ca3ed21a10573b856cc18a085035d4 /test/CodeGen | |
parent | c2b11baf5fdb26c2bf2c9b02dae9f0f0f61e9f1b (diff) | |
download | llvm-817812f61caa50ba3ce67ceb5a033cb69a3eea5c.tar.gz llvm-817812f61caa50ba3ce67ceb5a033cb69a3eea5c.tar.bz2 llvm-817812f61caa50ba3ce67ceb5a033cb69a3eea5c.tar.xz |
[X86] Improve the selection of SSE3/AVX addsub instructions.
This patch teaches the backend how to canonicalize a shuffle vectors
according to the rule:
- (shuffle (FADD A, B), (FSUB A, B), Mask) ->
(shuffle (FSUB A, -B), (FADD A, -B), Mask)
Where 'Mask' is:
<0,5,2,7> ;; for v4f32 and v4f64 shuffles.
<0,3> ;; for v2f64 shuffles.
<0,9,2,11,4,13,6,15> ;; for v8f32 shuffles.
In general, ISel only knows how to pattern-match a canonical
'fadd + fsub + blendi' dag node sequence into an ADDSUB instruction.
This new rule allows to convert a non-canonical dag sequence into a
canonical one that will be matched by a single ADDSUB at ISel stage.
The idea of converting a non-canonical ADDSUB into a canonical one by
swapping the first two operands of the shuffle, and then negating the
second operand of the FADD and FSUB, was originally proposed by Hal Finkel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211771 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r-- | test/CodeGen/X86/sse3-avx-addsub.ll | 157 |
1 files changed, 155 insertions, 2 deletions
diff --git a/test/CodeGen/X86/sse3-avx-addsub.ll b/test/CodeGen/X86/sse3-avx-addsub.ll index d7874e4145..8b6674312b 100644 --- a/test/CodeGen/X86/sse3-avx-addsub.ll +++ b/test/CodeGen/X86/sse3-avx-addsub.ll @@ -3,7 +3,7 @@ ; Test ADDSUB ISel patterns. -; All the functions below are obtained from the following source: +; Functions below are obtained from the following source: ; ; typedef double double2 __attribute__((ext_vector_type(2))); ; typedef double double4 __attribute__((ext_vector_type(4))); @@ -19,7 +19,7 @@ ; float8 test2(float8 A, float8 B) { ; float8 X = A - B; ; float8 Y = A + B; -; return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], [7]}; +; return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], Y[7]}; ; } ; ; double4 test3(double4 A, double4 B) { @@ -141,3 +141,156 @@ define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) { ; AVX: vaddsubpd ; CHECK-NEXT: ret +; Functions below are obtained from the following source: +; +; float4 test1(float4 A, float4 B) { +; float4 X = A + B; +; float4 Y = A - B; +; return (float4){X[0], Y[1], X[2], Y[3]}; +; } +; +; float8 test2(float8 A, float8 B) { +; float8 X = A + B; +; float8 Y = A - B; +; return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], Y[7]}; +; } +; +; double4 test3(double4 A, double4 B) { +; double4 X = A + B; +; double4 Y = A - B; +; return (double4){X[0], Y[1], X[2], Y[3]}; +; } +; +; double2 test4(double2 A, double2 B) { +; double2 X = A + B; +; double2 Y = A - B; +; return (double2){X[0], Y[1]}; +; } + +define <4 x float> @test5(<4 x float> %A, <4 x float> %B) { + %sub = fsub <4 x float> %A, %B + %add = fadd <4 x float> %A, %B + %vecinit6 = shufflevector <4 x float> %add, <4 x float> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x float> %vecinit6 +} +; CHECK-LABEL: test5 +; SSE: xorps +; SSE-NEXT: addsubps +; AVX: vxorps +; AVX-NEXT: vaddsubps +; CHECK: ret + + +define <8 x float> @test6(<8 x float> %A, <8 x float> %B) { + %sub = fsub <8 x float> %A, %B + %add = fadd <8 x float> %A, %B + %vecinit14 = shufflevector <8 x float> %add, <8 x float> %sub, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> + ret <8 x float> %vecinit14 +} +; CHECK-LABEL: test6 +; SSE: xorps +; SSE-NEXT: addsubps +; SSE: xorps +; SSE-NEXT: addsubps +; AVX: vxorps +; AVX-NEXT: vaddsubps +; AVX-NOT: vxorps +; AVX-NOT: vaddsubps +; CHECK: ret + + +define <4 x double> @test7(<4 x double> %A, <4 x double> %B) { + %sub = fsub <4 x double> %A, %B + %add = fadd <4 x double> %A, %B + %vecinit6 = shufflevector <4 x double> %add, <4 x double> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x double> %vecinit6 +} +; CHECK-LABEL: test7 +; SSE: xorpd +; SSE-NEXT: addsubpd +; SSE: xorpd +; SSE-NEXT: addsubpd +; AVX: vxorpd +; AVX-NEXT: vaddsubpd +; AVX-NOT: vxorpd +; AVX-NOT: vaddsubpd +; CHECK: ret + + +define <2 x double> @test8(<2 x double> %A, <2 x double> %B) #0 { + %add = fadd <2 x double> %A, %B + %sub = fsub <2 x double> %A, %B + %vecinit2 = shufflevector <2 x double> %add, <2 x double> %sub, <2 x i32> <i32 0, i32 3> + ret <2 x double> %vecinit2 +} +; CHECK-LABEL: test8 +; SSE: xorpd +; SSE-NEXT: addsubpd +; AVX: vxorpd +; AVX-NEXT: vaddsubpd +; CHECK: ret + + +define <4 x float> @test5b(<4 x float> %A, <4 x float> %B) { + %sub = fsub <4 x float> %A, %B + %add = fadd <4 x float> %B, %A + %vecinit6 = shufflevector <4 x float> %add, <4 x float> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x float> %vecinit6 +} +; CHECK-LABEL: test5 +; SSE: xorps +; SSE-NEXT: addsubps +; AVX: vxorps +; AVX-NEXT: vaddsubps +; CHECK: ret + + +define <8 x float> @test6b(<8 x float> %A, <8 x float> %B) { + %sub = fsub <8 x float> %A, %B + %add = fadd <8 x float> %B, %A + %vecinit14 = shufflevector <8 x float> %add, <8 x float> %sub, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> + ret <8 x float> %vecinit14 +} +; CHECK-LABEL: test6 +; SSE: xorps +; SSE-NEXT: addsubps +; SSE: xorps +; SSE-NEXT: addsubps +; AVX: vxorps +; AVX-NEXT: vaddsubps +; AVX-NOT: vxorps +; AVX-NOT: vaddsubps +; CHECK: ret + + +define <4 x double> @test7b(<4 x double> %A, <4 x double> %B) { + %sub = fsub <4 x double> %A, %B + %add = fadd <4 x double> %B, %A + %vecinit6 = shufflevector <4 x double> %add, <4 x double> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x double> %vecinit6 +} +; CHECK-LABEL: test7 +; SSE: xorpd +; SSE-NEXT: addsubpd +; SSE: xorpd +; SSE-NEXT: addsubpd +; AVX: vxorpd +; AVX-NEXT: vaddsubpd +; AVX-NOT: vxorpd +; AVX-NOT: vaddsubpd +; CHECK: ret + + +define <2 x double> @test8b(<2 x double> %A, <2 x double> %B) #0 { + %add = fadd <2 x double> %B, %A + %sub = fsub <2 x double> %A, %B + %vecinit2 = shufflevector <2 x double> %add, <2 x double> %sub, <2 x i32> <i32 0, i32 3> + ret <2 x double> %vecinit2 +} +; CHECK-LABEL: test8 +; SSE: xorpd +; SSE-NEXT: addsubpd +; AVX: vxorpd +; AVX-NEXT: vaddsubpd +; CHECK: ret + |