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| author | Evan Cheng <evan.cheng@apple.com> | 2011-11-14 19:48:55 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-11-14 19:48:55 +0000 |
| commit | 2a4410df44cd710e20b3f12873c35405830d66fb (patch) | |
| tree | 54cfc0134dfb9db90186e24b78f23932a37edf8b /test/CodeGen | |
| parent | a77214a4c43d7a0c49c348439c6887f28bd6d53d (diff) | |
| download | llvm-2a4410df44cd710e20b3f12873c35405830d66fb.tar.gz llvm-2a4410df44cd710e20b3f12873c35405830d66fb.tar.bz2 llvm-2a4410df44cd710e20b3f12873c35405830d66fb.tar.xz | |
Teach two-address pass to re-schedule two-address instructions (or the kill
instructions of the two-address operands) in order to avoid inserting copies.
This fixes the few regressions introduced when the two-address hack was
disabled (without regressing the improvements).
rdar://10422688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144559 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/X86/iv-users-in-other-loops.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/lsr-reuse-trunc.ll | 7 | ||||
| -rw-r--r-- | test/CodeGen/X86/sse3.ll | 24 |
3 files changed, 15 insertions, 18 deletions
diff --git a/test/CodeGen/X86/iv-users-in-other-loops.ll b/test/CodeGen/X86/iv-users-in-other-loops.ll index 4a6f5316a6..7f2bd75560 100644 --- a/test/CodeGen/X86/iv-users-in-other-loops.ll +++ b/test/CodeGen/X86/iv-users-in-other-loops.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86-64 -enable-lsr-nested -o %t ; RUN: not grep inc %t ; RUN: grep dec %t | count 2 -; RUN: grep addq %t | count 10 +; RUN: grep addq %t | count 12 ; RUN: not grep addb %t ; RUN: not grep leal %t ; RUN: not grep movq %t diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll index 5f5e0937a3..1f87089f80 100644 --- a/test/CodeGen/X86/lsr-reuse-trunc.ll +++ b/test/CodeGen/X86/lsr-reuse-trunc.ll @@ -4,14 +4,13 @@ ; Full strength reduction wouldn't reduce register pressure, so LSR should ; stick with indexing here. -; FIXME: This is worse off from disabling of scheduler 2-address hack. ; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]] -; CHECK: leaq 4(%rax), %{{rcx|r9}} ; CHECK: cvtdq2ps ; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]] ; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4) -; CHECK: cmpl %{{ecx|r9d}}, (%{{rdx|r8}}) -; CHECK: jg +; CHECK: addq $4, %rax +; CHECK: cmpl %eax, (%{{rdx|r8}}) +; CHECK-NEXT: jg define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind { entry: diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 291069d462..5ea1b4dff1 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -164,12 +164,12 @@ define internal void @t10() nounwind { store <4 x i16> %6, <4 x i16>* @g2, align 8 ret void ; X64: t10: -; X64: pextrw $4, [[X0:%xmm[0-9]+]], %eax -; X64: movlhps [[X1:%xmm[0-9]+]] -; X64: pshuflw $8, [[X1]], [[X2:%xmm[0-9]+]] -; X64: pinsrw $2, %eax, [[X2]] +; X64: pextrw $4, [[X0:%xmm[0-9]+]], %ecx ; X64: pextrw $6, [[X0]], %eax -; X64: pinsrw $3, %eax, [[X2]] +; X64: movlhps [[X0]], [[X0]] +; X64: pshuflw $8, [[X0]], [[X0]] +; X64: pinsrw $2, %ecx, [[X0]] +; X64: pinsrw $3, %eax, [[X0]] } @@ -232,10 +232,9 @@ entry: %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef > ret <8 x i16> %tmp8 ; X64: t15: -; X64: movdqa %xmm0, %xmm2 +; X64: pextrw $7, %xmm0, %eax ; X64: punpcklqdq %xmm1, %xmm0 ; X64: pshuflw $-128, %xmm0, %xmm0 -; X64: pextrw $7, %xmm2, %eax ; X64: pinsrw $2, %eax, %xmm0 ; X64: ret } @@ -248,12 +247,11 @@ entry: %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > ret <16 x i8> %tmp9 ; X64: t16: -; X64: movdqa %xmm1, %xmm2 -; X64: pslldq $2, %xmm2 -; X64: movd %xmm2, %eax -; X64: pinsrw $0, %eax, %xmm0 -; X64: pextrw $8, %xmm1, %eax -; X64: pextrw $1, %xmm2, %ecx +; X64: pextrw $8, %xmm0, %eax +; X64: pslldq $2, %xmm0 +; X64: movd %xmm0, %ecx +; X64: pextrw $1, %xmm0, %edx +; X64: pinsrw $0, %ecx, %xmm0 ; X64: ret } |