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author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-11-26 10:53:16 +0000 |
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committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-11-26 10:53:16 +0000 |
commit | 396e080b3467ccdcbbfb908f9405e7dd134d5c8a (patch) | |
tree | 10ea35fa3144148755bed187dbd1f6eb3f282c7f /test/CodeGen | |
parent | 7c6be4d5586aa365c8f52289ffddf57b87da4da7 (diff) | |
download | llvm-396e080b3467ccdcbbfb908f9405e7dd134d5c8a.tar.gz llvm-396e080b3467ccdcbbfb908f9405e7dd134d5c8a.tar.bz2 llvm-396e080b3467ccdcbbfb908f9405e7dd134d5c8a.tar.xz |
[SystemZ] Fix incorrect use of RISBG for a zero-extended right shift
We would wrongly transform the testcase into the equivalent of an AND with 1.
The problem was that, when testing whether the shifted-in bits of the right
shift were significant, we used the width of the final zero-extended result
rather than the width of the shifted value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195731 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r-- | test/CodeGen/SystemZ/risbg-01.ll | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll index 8a5d4874f6..a4d11fdae5 100644 --- a/test/CodeGen/SystemZ/risbg-01.ll +++ b/test/CodeGen/SystemZ/risbg-01.ll @@ -456,3 +456,17 @@ define i64 @f40(i64 %foo, i64 *%dest) { %and = and i64 %shl, 2147483647 ret i64 %and } + +; In this case the sign extension is converted to a pair of 32-bit shifts, +; which is then extended to 64 bits. We previously used the wrong bit size +; when testing whether the shifted-in bits of the shift right were significant. +define i64 @f41(i1 %x) { +; CHECK-LABEL: f41: +; CHECK: sll %r2, 31 +; CHECK: sra %r2, 31 +; CHECK: llgcr %r2, %r2 +; CHECK: br %r14 + %ext = sext i1 %x to i8 + %ext2 = zext i8 %ext to i64 + ret i64 %ext2 +} |