ARM64: hexify printing various immediate operands

This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they
accept weird shifts which are more naturally understandable in hex notation).

Also changes BRK/HINT etc, which is probably a neutral change, but easier than
the alternative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 17 insertions, 17 deletions

diff --git a/test/CodeGen/ARM64/aarch64-neon-copy.ll b/test/CodeGen/ARM64/aarch64-neon-copy.ll
index ce851525da..3b4cc6cc4f 100644
--- a/test/CodeGen/ARM64/aarch64-neon-copy.ll
+++ b/test/CodeGen/ARM64/aarch64-neon-copy.ll
@@ -1369,7 +1369,7 @@ define <4 x i16> @concat_vector_v4i16_const() {
 
 define <4 x i16> @concat_vector_v4i16_const_one() {
 ; CHECK-LABEL: concat_vector_v4i16_const_one:
-; CHECK: movi {{v[0-9]+}}.4h, #1
+; CHECK: movi {{v[0-9]+}}.4h, #0x1
  %r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <4 x i32> zeroinitializer
  ret <4 x i16> %r
 }
@@ -1397,7 +1397,7 @@ define <8 x i16> @concat_vector_v8i16_const() {
 
 define <8 x i16> @concat_vector_v8i16_const_one() {
 ; CHECK-LABEL: concat_vector_v8i16_const_one:
-; CHECK: movi {{v[0-9]+}}.8h, #1
+; CHECK: movi {{v[0-9]+}}.8h, #0x1
  %r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <8 x i32> zeroinitializer
  ret <8 x i16> %r
 }
diff --git a/test/CodeGen/ARM64/fast-isel.ll b/test/CodeGen/ARM64/fast-isel.ll
index ba718d3a95..0194b3a6c2 100644
--- a/test/CodeGen/ARM64/fast-isel.ll
+++ b/test/CodeGen/ARM64/fast-isel.ll
@@ -87,7 +87,7 @@ entry:
 
 define void @t6() nounwind {
 ; CHECK: t6
-; CHECK: brk #1
+; CHECK: brk #0x1
   tail call void @llvm.trap()
   ret void
 }
diff --git a/test/CodeGen/ARM64/fcopysign.ll b/test/CodeGen/ARM64/fcopysign.ll
index 094ce7aa5b..66241df944 100644
--- a/test/CodeGen/ARM64/fcopysign.ll
+++ b/test/CodeGen/ARM64/fcopysign.ll
@@ -5,7 +5,7 @@
 define float @test1(float %x, float %y) nounwind {
 entry:
 ; CHECK-LABEL: test1:
-; CHECK: movi.4s	v2, #128, lsl #24
+; CHECK: movi.4s	v2, #0x80, lsl #24
 ; CHECK: bit.16b	v0, v1, v2
   %0 = tail call float @copysignf(float %x, float %y) nounwind readnone
   ret float %0
@@ -37,7 +37,7 @@ define float @test4() nounwind {
 entry:
 ; CHECK-LABEL: test4:
 ; CHECK: fcvt s0, d0
-; CHECK: movi.4s v[[CONST:[0-9]+]], #128, lsl #24
+; CHECK: movi.4s v[[CONST:[0-9]+]], #0x80, lsl #24
 ; CHECK: bit.16b v{{[0-9]+}}, v0, v[[CONST]]
   %0 = tail call double (...)* @bar() nounwind
   %1 = fptrunc double %0 to float
diff --git a/test/CodeGen/ARM64/trap.ll b/test/CodeGen/ARM64/trap.ll
index c9e0beabfc..5e99c32c57 100644
--- a/test/CodeGen/ARM64/trap.ll
+++ b/test/CodeGen/ARM64/trap.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm64 | FileCheck %s
 define void @foo() nounwind {
 ; CHECK: foo
-; CHECK: brk #1
+; CHECK: brk #0x1
   tail call void @llvm.trap()
   ret void
 }
diff --git a/test/CodeGen/ARM64/vector-ext.ll b/test/CodeGen/ARM64/vector-ext.ll
index 88889fdef3..9cc0555d8c 100644
--- a/test/CodeGen/ARM64/vector-ext.ll
+++ b/test/CodeGen/ARM64/vector-ext.ll
@@ -2,7 +2,7 @@
 
 ;CHECK: @func30
 ;CHECK: ushll.4s  v0, v0, #0
-;CHECK: movi.4s v1, #1
+;CHECK: movi.4s v1, #0x1
 ;CHECK: and.16b v0, v0, v1
 ;CHECK: str  q0, [x0]
 ;CHECK: ret
diff --git a/test/CodeGen/ARM64/vector-imm.ll b/test/CodeGen/ARM64/vector-imm.ll
index f1fc3ccf84..2a9450f4e2 100644
--- a/test/CodeGen/ARM64/vector-imm.ll
+++ b/test/CodeGen/ARM64/vector-imm.ll
@@ -50,35 +50,35 @@ define <2 x double> @foo(<2 x double> %bar) nounwind {
 define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t1:
-; CHECK: movi.4s v0, #75
+; CHECK: movi.4s v0, #0x4b
   ret <4 x i32> <i32 75, i32 75, i32 75, i32 75>
 }
 
 define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t2:
-; CHECK: movi.4s v0, #75, lsl #8
+; CHECK: movi.4s v0, #0x4b, lsl #8
   ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200>
 }
 
 define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t3:
-; CHECK: movi.4s v0, #75, lsl #16
+; CHECK: movi.4s v0, #0x4b, lsl #16
   ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200>
 }
 
 define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t4:
-; CHECK: movi.4s v0, #75, lsl #24
+; CHECK: movi.4s v0, #0x4b, lsl #24
   ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
 }
 
 define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_8h_imm_t5:
-; CHECK: movi.8h v0, #75
+; CHECK: movi.8h v0, #0x4b
   ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75>
 }
 
@@ -86,28 +86,28 @@ entry:
 define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_8h_imm_t6:
-; CHECK: movi.8h v0, #75, lsl #8
+; CHECK: movi.8h v0, #0x4b, lsl #8
   ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200>
 }
 
 define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t7:
-; CHECK: movi.4s v0, #75, msl #8
+; CHECK: movi.4s v0, #0x4b, msl #8
 ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455>
 }
 
 define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_4s_imm_t8:
-; CHECK: movi.4s v0, #75, msl #16
+; CHECK: movi.4s v0, #0x4b, msl #16
 ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735>
 }
 
 define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: movi_16b_imm_t9:
-; CHECK: movi.16b v0, #75
+; CHECK: movi.16b v0, #0x4b
 ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75,
                i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75>
 }
diff --git a/test/CodeGen/ARM64/vshuffle.ll b/test/CodeGen/ARM64/vshuffle.ll
index fb1227daad..62fd96102d 100644
--- a/test/CodeGen/ARM64/vshuffle.ll
+++ b/test/CodeGen/ARM64/vshuffle.ll
@@ -15,7 +15,7 @@
 ; CHECK:  .byte   0                       ; 0x0
 ; CHECK: test1
 ; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI0_0
-; CHECK: movi.8h v[[REG1:[0-9]+]], #1, lsl #8
+; CHECK: movi.8h v[[REG1:[0-9]+]], #0x1, lsl #8
 ; CHECK: tbl.8b  v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
 define <8 x i1> @test1() {
 entry: