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| author | Chad Rosier <mcrosier@apple.com> | 2011-06-14 22:29:10 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2011-06-14 22:29:10 +0000 |
| commit | 92bcd96bbcf42911a76570cc0974e513bc7f261d (patch) | |
| tree | f7aa5be2ae7bfc3418f06248d0efe73406e1648b /test/CodeGen | |
| parent | 1c61990b2daa77f3444eb2b6d8157cdc805ce22f (diff) | |
| download | llvm-92bcd96bbcf42911a76570cc0974e513bc7f261d.tar.gz llvm-92bcd96bbcf42911a76570cc0974e513bc7f261d.tar.bz2 llvm-92bcd96bbcf42911a76570cc0974e513bc7f261d.tar.xz | |
When pattern matching during instruction selection make sure shl x,1 is not
converted to add x,x if x is a undef. add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133022 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/X86/shl_undef.ll | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/test/CodeGen/X86/shl_undef.ll b/test/CodeGen/X86/shl_undef.ll new file mode 100644 index 0000000000..f0c6402a9c --- /dev/null +++ b/test/CodeGen/X86/shl_undef.ll @@ -0,0 +1,53 @@ +; RUN: llc < %s -O1 -mtriple=i386-apple-darwin | FileCheck %s +; +; Interesting test case where %tmp1220 = xor i32 %tmp862, %tmp592 and +; %tmp1676 = xor i32 %tmp1634, %tmp1530 have zero demanded bits after +; TargetLoweringOpt pass. These are changed to undef and in turn +; the successor shl(s) become shl undef, 1. This pattern then matches +; shl x, 1 -> add x, x. add undef, undef doesn't guarentee the low +; order bit is zero and is incorrect. +; +; See rdar://9453156 and rdar://9487392. +; + +; CHECK-NOT: shl +define i32 @foo(i8* %a0, i32* %a2) nounwind { +entry: + %tmp0 = alloca i8 + %tmp1 = alloca i32 + store i8 1, i8* %tmp0 + %tmp921.i7845 = load i8* %a0, align 1 + %tmp309 = xor i8 %tmp921.i7845, 104 + %tmp592 = zext i8 %tmp309 to i32 + %tmp862 = xor i32 1293461297, %tmp592 + %tmp1220 = xor i32 %tmp862, %tmp592 + %tmp1506 = shl i32 %tmp1220, 1 + %tmp1530 = sub i32 %tmp592, %tmp1506 + %tmp1557 = sub i32 %tmp1530, 542767629 + %tmp1607 = and i32 %tmp1557, 1 + store i32 %tmp1607, i32* %tmp1 + %tmp1634 = and i32 %tmp1607, 2080309246 + %tmp1676 = xor i32 %tmp1634, %tmp1530 + %tmp1618 = shl i32 %tmp1676, 1 + %tmp1645 = sub i32 %tmp862, %tmp1618 + %tmp1697 = and i32 %tmp1645, 1 + store i32 %tmp1697, i32* %a2 + ret i32 %tmp1607 +} + +; CHECK-NOT: shl +; shl undef, 0 -> undef +define i32 @foo2_undef() nounwind { +entry: + %tmp2 = shl i32 undef, 0; + ret i32 %tmp2 +} + +; CHECK-NOT: shl +; shl undef, x -> 0 +define i32 @foo1_undef(i32* %a0) nounwind { +entry: + %tmp1 = load i32* %a0, align 1 + %tmp2 = shl i32 undef, %tmp1; + ret i32 %tmp2 +} |