diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-17 00:25:41 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-17 00:25:41 +0000 |
| commit | 94e472832f30320d273f5630044c6bbd626e9949 (patch) | |
| tree | e7efab07326361a7e2a73483b0cf2820acf5f2e5 /test/CodeGen | |
| parent | 8b149cbfc6cb420016eff52f6380d1eba5daea20 (diff) | |
| download | llvm-94e472832f30320d273f5630044c6bbd626e9949.tar.gz llvm-94e472832f30320d273f5630044c6bbd626e9949.tar.bz2 llvm-94e472832f30320d273f5630044c6bbd626e9949.tar.xz | |
Initial implementation of MipsTargetLowering::isLegalAddressingMode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168230 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/Mips/addressing-mode.ll | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/addressing-mode.ll b/test/CodeGen/Mips/addressing-mode.ll new file mode 100644 index 0000000000..ea76dde82d --- /dev/null +++ b/test/CodeGen/Mips/addressing-mode.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +@g0 = common global i32 0, align 4 +@g1 = common global i32 0, align 4 + +; Check that LSR doesn't choose a solution with a formula "reg + 4*reg". +; +; CHECK: $BB0_2: +; CHECK-NOT: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 + +define i32 @f0(i32 %n, i32 %m, [256 x i32]* nocapture %a, [256 x i32]* nocapture %b) nounwind readonly { +entry: + br label %for.cond1.preheader + +for.cond1.preheader: + %s.022 = phi i32 [ 0, %entry ], [ %add7, %for.inc9 ] + %i.021 = phi i32 [ 0, %entry ], [ %add10, %for.inc9 ] + br label %for.body3 + +for.body3: + %s.120 = phi i32 [ %s.022, %for.cond1.preheader ], [ %add7, %for.body3 ] + %j.019 = phi i32 [ 0, %for.cond1.preheader ], [ %add8, %for.body3 ] + %arrayidx4 = getelementptr inbounds [256 x i32]* %a, i32 %i.021, i32 %j.019 + %0 = load i32* %arrayidx4, align 4 + %arrayidx6 = getelementptr inbounds [256 x i32]* %b, i32 %i.021, i32 %j.019 + %1 = load i32* %arrayidx6, align 4 + %add = add i32 %0, %s.120 + %add7 = add i32 %add, %1 + %add8 = add nsw i32 %j.019, %m + %cmp2 = icmp slt i32 %add8, 64 + br i1 %cmp2, label %for.body3, label %for.inc9 + +for.inc9: + %add10 = add nsw i32 %i.021, %n + %cmp = icmp slt i32 %add10, 64 + br i1 %cmp, label %for.cond1.preheader, label %for.end11 + +for.end11: + ret i32 %add7 +} + |