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authorBenjamin Kramer <benny.kra@googlemail.com>2014-04-26 14:12:19 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2014-04-26 14:12:19 +0000
commit9f2c21871ce2bc49e715ea1cf934ac10746ccf70 (patch)
treeaf4dbeffac6d7edbfb0781d2628719769f8a6b5c /test/CodeGen
parentfb625eadf9b7257a3cfb887da3c1b0bcf8a749c7 (diff)
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X86: Lower SMUL_LOHI of v4i32 to pmuldq when SSE4.1 is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207318 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r--test/CodeGen/X86/vector-idiv.ll51
1 files changed, 49 insertions, 2 deletions
diff --git a/test/CodeGen/X86/vector-idiv.ll b/test/CodeGen/X86/vector-idiv.ll
index 0d43b96163..06af3434b1 100644
--- a/test/CodeGen/X86/vector-idiv.ll
+++ b/test/CodeGen/X86/vector-idiv.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=x86-64 -mcpu=core2 < %s | FileCheck %s -check-prefix=SSE
+; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s -check-prefix=SSE
; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX
define <4 x i32> @test1(<4 x i32> %a) {
@@ -103,4 +103,51 @@ define <16 x i16> @test6(<16 x i16> %a) {
; AVX-NOT: vpmulhw
}
-; TODO: sdiv -> pmuldq
+define <16 x i8> @test7(<16 x i8> %a) {
+ %div = sdiv <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
+ ret <16 x i8> %div
+}
+
+define <4 x i32> @test8(<4 x i32> %a) {
+ %div = sdiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
+ ret <4 x i32> %div
+
+; SSE-LABEL: test8:
+; SSE: pmuldq
+; SSE: pshufd $57
+; SSE: pmuldq
+; SSE: shufps $-35
+; SSE: pshufd $-40
+; SSE: padd
+; SSE: psrld $31
+; SSE: psrad $2
+; SSE: padd
+
+; AVX-LABEL: test8:
+; AVX: vpmuldq
+; AVX: vpshufd $57
+; AVX: vpmuldq
+; AVX: vshufps $-35
+; AVX: vpshufd $-40
+; AVX: vpadd
+; AVX: vpsrld $31
+; AVX: vpsrad $2
+; AVX: vpadd
+}
+
+define <8 x i32> @test9(<8 x i32> %a) {
+ %div = sdiv <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
+ ret <8 x i32> %div
+
+; AVX-LABEL: test9:
+; AVX: vpermd
+; AVX: vpmuldq
+; AVX: vshufps $-35
+; AVX: vpmuldq
+; AVX: vshufps $-35
+; AVX: vpshufd $-40
+; AVX: vpadd
+; AVX: vpsrld $31
+; AVX: vpsrad $2
+; AVX: vpadd
+}