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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-07-12 18:06:44 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-07-12 18:06:44 +0000 |
| commit | b619dd5d5b69ba9f4571a96e1a96d09d8aed03a7 (patch) | |
| tree | 79411ae481a896f857d5a454961479a75289eac9 /test/CodeGen | |
| parent | 2494dfcf1795a9bd28030d04cf2fb15e5c3b0f33 (diff) | |
| download | llvm-b619dd5d5b69ba9f4571a96e1a96d09d8aed03a7.tar.gz llvm-b619dd5d5b69ba9f4571a96e1a96d09d8aed03a7.tar.bz2 llvm-b619dd5d5b69ba9f4571a96e1a96d09d8aed03a7.tar.xz | |
X86: Shrink certain forms of movsx.
In particular:
movsbw %al, %ax --> cbtw
movswl %ax, %eax --> cwtl
movslq %eax, %rax --> cltq
According to Intel's manual those have the same performance characteristics but
come with a smaller encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186174 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/X86/fast-isel-ret-ext.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/mcinst-lowering.ll | 18 | ||||
| -rw-r--r-- | test/CodeGen/X86/shl_elim.ll | 9 | ||||
| -rw-r--r-- | test/CodeGen/X86/widen_conv-2.ll | 4 |
4 files changed, 27 insertions, 6 deletions
diff --git a/test/CodeGen/X86/fast-isel-ret-ext.ll b/test/CodeGen/X86/fast-isel-ret-ext.ll index fd768cb9b3..395ad1e616 100644 --- a/test/CodeGen/X86/fast-isel-ret-ext.ll +++ b/test/CodeGen/X86/fast-isel-ret-ext.ll @@ -26,7 +26,7 @@ define signext i16 @test4(i32 %y) nounwind { %conv = trunc i32 %y to i16 ret i16 %conv ; CHECK: test4: - ; CHECK: movswl {{.*}}, %eax + ; CHECK: {{(movswl.%.x, %eax|cwtl)}} } define zeroext i1 @test5(i32 %y) nounwind { diff --git a/test/CodeGen/X86/mcinst-lowering.ll b/test/CodeGen/X86/mcinst-lowering.ll index 1ef5a971ba..391f9398f0 100644 --- a/test/CodeGen/X86/mcinst-lowering.ll +++ b/test/CodeGen/X86/mcinst-lowering.ll @@ -24,3 +24,21 @@ if.end: ; preds = %entry return: ; preds = %entry ret i32 0 } + +define i32 @f1() nounwind { + %ax = tail call i16 asm sideeffect "", "={ax},~{dirflag},~{fpsr},~{flags}"() + %conv = sext i16 %ax to i32 + ret i32 %conv + +; CHECK: f1: +; CHECK: cwtl ## encoding: [0x98] +} + +define i64 @f2() nounwind { + %eax = tail call i32 asm sideeffect "", "={ax},~{dirflag},~{fpsr},~{flags}"() + %conv = sext i32 %eax to i64 + ret i64 %conv + +; CHECK: f2: +; CHECK: cltq ## encoding: [0x48,0x98] +} diff --git a/test/CodeGen/X86/shl_elim.ll b/test/CodeGen/X86/shl_elim.ll index 83e1eb5c39..e99ecac872 100644 --- a/test/CodeGen/X86/shl_elim.ll +++ b/test/CodeGen/X86/shl_elim.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -march=x86 | grep "movl 8(.esp), %eax" -; RUN: llc < %s -march=x86 | grep "shrl .eax" -; RUN: llc < %s -march=x86 | grep "movswl .ax, .eax" +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @test1(i64 %a) nounwind { %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1] @@ -9,5 +7,10 @@ define i32 @test1(i64 %a) nounwind { %tmp45 = trunc i32 %tmp410 to i16 ; <i16> [#uses=1] %tmp456 = sext i16 %tmp45 to i32 ; <i32> [#uses=1] ret i32 %tmp456 + +; CHECK: test1: +; CHECK: movl 8(%esp), %eax +; CHECK: shrl %eax +; CHECK: cwtl } diff --git a/test/CodeGen/X86/widen_conv-2.ll b/test/CodeGen/X86/widen_conv-2.ll index 969cb512be..db8fa93dc7 100644 --- a/test/CodeGen/X86/widen_conv-2.ll +++ b/test/CodeGen/X86/widen_conv-2.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -; CHECK: movswl -; CHECK: movswl +; CHECK: cwtl +; CHECK: cwtl ; sign extension v2i32 to v2i16 |