[AArch64] Overload NEON signed/unsigned floating-point convert to fixed-point

and fixed-point convert to floating-point LLVM AArch64 intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196963 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 16 insertions, 16 deletions

diff --git a/test/CodeGen/AArch64/neon-scalar-cvt.ll b/test/CodeGen/AArch64/neon-scalar-cvt.ll
index 392b911379..ef91c2e4a8 100644
--- a/test/CodeGen/AArch64/neon-scalar-cvt.ll
+++ b/test/CodeGen/AArch64/neon-scalar-cvt.ll
@@ -49,89 +49,89 @@ define float @test_vcvts_n_f32_s32(i32 %a) {
 ; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
 entry:
   %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
-  %0 = call float @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32> %vcvtf, i32 1)
+  %0 = call float @llvm.aarch64.neon.vcvtfxs2fp.n.f32.v1i32(<1 x i32> %vcvtf, i32 1)
   ret float %0
 }
 
-declare float @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32>, i32)
+declare float @llvm.aarch64.neon.vcvtfxs2fp.n.f32.v1i32(<1 x i32>, i32)
 
 define double @test_vcvtd_n_f64_s64(i64 %a) {
 ; CHECK: test_vcvtd_n_f64_s64
 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
 entry:
   %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
-  %0 = call double @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64> %vcvtf, i32 1)
+  %0 = call double @llvm.aarch64.neon.vcvtfxs2fp.n.f64.v1i64(<1 x i64> %vcvtf, i32 1)
   ret double %0
 }
 
-declare double @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64>, i32)
+declare double @llvm.aarch64.neon.vcvtfxs2fp.n.f64.v1i64(<1 x i64>, i32)
 
 define float @test_vcvts_n_f32_u32(i32 %a) {
 ; CHECK: test_vcvts_n_f32_u32
 ; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
 entry:
   %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
-  %0 = call float @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32> %vcvtf, i32 1)
+  %0 = call float @llvm.aarch64.neon.vcvtfxu2fp.n.f32.v1i32(<1 x i32> %vcvtf, i32 1)
   ret float %0
 }
 
-declare float @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32>, i32)
+declare float @llvm.aarch64.neon.vcvtfxu2fp.n.f32.v1i32(<1 x i32>, i32)
 
 define double @test_vcvtd_n_f64_u64(i64 %a) {
 ; CHECK: test_vcvtd_n_f64_u64
 ; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
 entry:
   %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
-  %0 = call double @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64> %vcvtf, i32 1)
+  %0 = call double @llvm.aarch64.neon.vcvtfxu2fp.n.f64.v1i64(<1 x i64> %vcvtf, i32 1)
   ret double %0
 }
 
-declare double @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64>, i32)
+declare double @llvm.aarch64.neon.vcvtfxu2fp.n.f64.v1i64(<1 x i64>, i32)
 
 define i32 @test_vcvts_n_s32_f32(float %a) {
 ; CHECK: test_vcvts_n_s32_f32
 ; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #1
 entry:
   %fcvtzs = insertelement <1 x float> undef, float %a, i32 0
-  %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float> %fcvtzs, i32 1)
+  %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.v1f32(<1 x float> %fcvtzs, i32 1)
   %0 = extractelement <1 x i32> %fcvtzs1, i32 0
   ret i32 %0
 }
 
-declare <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float>, i32)
+declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.v1f32(<1 x float>, i32)
 
 define i64 @test_vcvtd_n_s64_f64(double %a) {
 ; CHECK: test_vcvtd_n_s64_f64
 ; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #1
 entry:
   %fcvtzs = insertelement <1 x double> undef, double %a, i32 0
-  %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double> %fcvtzs, i32 1)
+  %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.v1f64(<1 x double> %fcvtzs, i32 1)
   %0 = extractelement <1 x i64> %fcvtzs1, i32 0
   ret i64 %0
 }
 
-declare <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double>, i32)
+declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.v1f64(<1 x double>, i32)
 
 define i32 @test_vcvts_n_u32_f32(float %a) {
 ; CHECK: test_vcvts_n_u32_f32
 ; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #32
 entry:
   %fcvtzu = insertelement <1 x float> undef, float %a, i32 0
-  %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float> %fcvtzu, i32 32)
+  %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.v1f32(<1 x float> %fcvtzu, i32 32)
   %0 = extractelement <1 x i32> %fcvtzu1, i32 0
   ret i32 %0
 }
 
-declare <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float>, i32)
+declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.v1f32(<1 x float>, i32)
 
 define i64 @test_vcvtd_n_u64_f64(double %a) {
 ; CHECK: test_vcvtd_n_u64_f64
 ; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #64
 entry:
   %fcvtzu = insertelement <1 x double> undef, double %a, i32 0
-  %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double> %fcvtzu, i32 64)
+  %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.v1f64(<1 x double> %fcvtzu, i32 64)
   %0 = extractelement <1 x i64> %fcvtzu1, i32 0
   ret i64 %0
 }
 
-declare <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double>, i32)
+declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.v1f64(<1 x double>, i32)