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| author | Che-Liang Chiou <clchiou@gmail.com> | 2010-12-06 04:00:03 +0000 |
|---|---|---|
| committer | Che-Liang Chiou <clchiou@gmail.com> | 2010-12-06 04:00:03 +0000 |
| commit | f9644867712c531427567ca4f936f507cd34f1b1 (patch) | |
| tree | aa4c1da71c4347c6a8eae61558a02c41e9812098 /test/CodeGen | |
| parent | f8803fe4177739f9a6900198f601808eb27934d9 (diff) | |
| download | llvm-f9644867712c531427567ca4f936f507cd34f1b1.tar.gz llvm-f9644867712c531427567ca4f936f507cd34f1b1.tar.bz2 llvm-f9644867712c531427567ca4f936f507cd34f1b1.tar.xz | |
ptx: add shift instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120982 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/PTX/shl.ll | 22 | ||||
| -rw-r--r-- | test/CodeGen/PTX/shr.ll | 43 |
2 files changed, 65 insertions, 0 deletions
diff --git a/test/CodeGen/PTX/shl.ll b/test/CodeGen/PTX/shl.ll new file mode 100644 index 0000000000..b564b43ab9 --- /dev/null +++ b/test/CodeGen/PTX/shl.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define ptx_device i32 @t1(i32 %x, i32 %y) { +; CHECK: shl.b32 r0, r1, r2 + %z = shl i32 %x, %y +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t2(i32 %x) { +; CHECK: shl.b32 r0, r1, 3 + %z = shl i32 %x, 3 +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t3(i32 %x) { +; CHECK: shl.b32 r0, 3, r1 + %z = shl i32 3, %x +; CHECK: ret; + ret i32 %z +} diff --git a/test/CodeGen/PTX/shr.ll b/test/CodeGen/PTX/shr.ll new file mode 100644 index 0000000000..3f8ade862b --- /dev/null +++ b/test/CodeGen/PTX/shr.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define ptx_device i32 @t1(i32 %x, i32 %y) { +; CHECK: shr.u32 r0, r1, r2 + %z = lshr i32 %x, %y +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t2(i32 %x) { +; CHECK: shr.u32 r0, r1, 3 + %z = lshr i32 %x, 3 +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t3(i32 %x) { +; CHECK: shr.u32 r0, 3, r1 + %z = lshr i32 3, %x +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t4(i32 %x, i32 %y) { +; CHECK: shr.s32 r0, r1, r2 + %z = ashr i32 %x, %y +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t5(i32 %x) { +; CHECK: shr.s32 r0, r1, 3 + %z = ashr i32 %x, 3 +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t6(i32 %x) { +; CHECK: shr.s32 r0, -3, r1 + %z = ashr i32 -3, %x +; CHECK: ret; + ret i32 %z +} |