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| author | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
| commit | 7b837d8c75f78fe55c9b348b9ec2281169a48d2a (patch) | |
| tree | e8e01e73cf4d0723a13e49e4b5d8a66f896d184f /test/MC/ARM64/basic-a64-instructions.s | |
| parent | 69bd9577fc423edea13479eaacf7b1844faa6c6a (diff) | |
| download | llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.gz llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.bz2 llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.xz | |
ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM64/basic-a64-instructions.s')
| -rw-r--r-- | test/MC/ARM64/basic-a64-instructions.s | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/MC/ARM64/basic-a64-instructions.s b/test/MC/ARM64/basic-a64-instructions.s new file mode 100644 index 0000000000..99b438d64b --- /dev/null +++ b/test/MC/ARM64/basic-a64-instructions.s @@ -0,0 +1,18 @@ +// RUN: llvm-mc -triple arm64 -show-encoding < %s | FileCheck %s + + crc32b w5, w7, w20 + crc32h w28, wzr, w30 + crc32w w0, w1, w2 + crc32x w7, w9, x20 + crc32cb w9, w5, w4 + crc32ch w13, w17, w25 + crc32cw wzr, w3, w5 + crc32cx w18, w16, xzr +// CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a] +// CHECK: crc32h w28, wzr, w30 // encoding: [0xfc,0x47,0xde,0x1a] +// CHECK: crc32w w0, w1, w2 // encoding: [0x20,0x48,0xc2,0x1a] +// CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a] +// CHECK: crc32cb w9, w5, w4 // encoding: [0xa9,0x50,0xc4,0x1a] +// CHECK: crc32ch w13, w17, w25 // encoding: [0x2d,0x56,0xd9,0x1a] +// CHECK: crc32cw wzr, w3, w5 // encoding: [0x7f,0x58,0xc5,0x1a] +// CHECK: crc32cx w18, w16, xzr // encoding: [0x12,0x5e,0xdf,0x9a] |