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| author | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-03-29 10:18:08 +0000 |
| commit | 7b837d8c75f78fe55c9b348b9ec2281169a48d2a (patch) | |
| tree | e8e01e73cf4d0723a13e49e4b5d8a66f896d184f /test/MC/Disassembler/ARM64/branch.txt | |
| parent | 69bd9577fc423edea13479eaacf7b1844faa6c6a (diff) | |
| download | llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.gz llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.bz2 llvm-7b837d8c75f78fe55c9b348b9ec2281169a48d2a.tar.xz | |
ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler/ARM64/branch.txt')
| -rw-r--r-- | test/MC/Disassembler/ARM64/branch.txt | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM64/branch.txt b/test/MC/Disassembler/ARM64/branch.txt new file mode 100644 index 0000000000..c5b254b736 --- /dev/null +++ b/test/MC/Disassembler/ARM64/branch.txt @@ -0,0 +1,75 @@ +# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s + +#----------------------------------------------------------------------------- +# Unconditional branch (register) instructions. +#----------------------------------------------------------------------------- + + 0xc0 0x03 0x5f 0xd6 +# CHECK: ret + 0x20 0x00 0x5f 0xd6 +# CHECK: ret x1 + 0xe0 0x03 0xbf 0xd6 +# CHECK: drps + 0xe0 0x03 0x9f 0xd6 +# CHECK: eret + 0xa0 0x00 0x1f 0xd6 +# CHECK: br x5 + 0x20 0x01 0x3f 0xd6 +# CHECK: blr x9 + 0x0B 0x00 0x18 0x37 +# CHECK: tbnz w11, #3, #0 + +#----------------------------------------------------------------------------- +# Exception generation instructions. +#----------------------------------------------------------------------------- + + 0x20 0x00 0x20 0xd4 +# CHECK: brk #1 + 0x41 0x00 0xa0 0xd4 +# CHECK: dcps1 #2 + 0x62 0x00 0xa0 0xd4 +# CHECK: dcps2 #3 + 0x83 0x00 0xa0 0xd4 +# CHECK: dcps3 #4 + 0xa0 0x00 0x40 0xd4 +# CHECK: hlt #5 + 0xc2 0x00 0x00 0xd4 +# CHECK: hvc #6 + 0xe3 0x00 0x00 0xd4 +# CHECK: smc #7 + 0x01 0x01 0x00 0xd4 +# CHECK: svc #8 + +#----------------------------------------------------------------------------- +# PC-relative branches (both positive and negative displacement) +#----------------------------------------------------------------------------- + + 0x07 0x00 0x00 0x14 +# CHECK: b #28 + 0x06 0x00 0x00 0x94 +# CHECK: bl #24 + 0xa1 0x00 0x00 0x54 +# CHECK: b.ne #20 + 0x80 0x00 0x08 0x36 +# CHECK: tbz w0, #1, #16 + 0xe1 0xff 0xf7 0x36 +# CHECK: tbz w1, #30, #-4 + 0x60 0x00 0x08 0x37 +# CHECK: tbnz w0, #1, #12 + 0x40 0x00 0x00 0xb4 +# CHECK: cbz x0, #8 + 0x20 0x00 0x00 0xb5 +# CHECK: cbnz x0, #4 + 0x1f 0x20 0x03 0xd5 +# CHECK: nop + 0xff 0xff 0xff 0x17 +# CHECK: b #-4 + 0xc1 0xff 0xff 0x54 +# CHECK: b.ne #-8 + 0xa0 0xff 0x0f 0x36 +# CHECK: tbz w0, #1, #-12 + 0x80 0xff 0xff 0xb4 +# CHECK: cbz x0, #-16 + 0x1f 0x20 0x03 0xd5 +# CHECK: nop + |