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author | Owen Anderson <resistor@mac.com> | 2011-10-20 22:23:58 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2011-10-20 22:23:58 +0000 |
commit | cd20c58e980552daef182247005cf905fe8b06ba (patch) | |
tree | f5ab0c7d1d88c3acc6bfc48c2ae2d5ce31d89608 /test/MC | |
parent | fe0748d696a69b66e11fce0256663070c0bb7e70 (diff) | |
download | llvm-cd20c58e980552daef182247005cf905fe8b06ba.tar.gz llvm-cd20c58e980552daef182247005cf905fe8b06ba.tar.bz2 llvm-cd20c58e980552daef182247005cf905fe8b06ba.tar.xz |
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
-rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 36 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 6 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM/basic-arm-instructions.txt | 54 |
3 files changed, 73 insertions, 23 deletions
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 6640882024..55d9f02619 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -928,15 +928,15 @@ Lforward: @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_nzcvqg, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] -@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3] -@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x20,0xe3] -@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x20,0xe3] -@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3] -@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3] -@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] -@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3] -@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] -@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x21,0xe3] +@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x22,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2e,0xe3] +@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3] +@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3] +@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3] msr apsr, r0 msr apsr_g, r0 @@ -958,15 +958,15 @@ Lforward: @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] @ CHECK: msr APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] -@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1] -@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x20,0xe1] -@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x20,0xe1] -@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1] -@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1] -@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] -@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1] -@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] -@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1] +@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1] +@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1] +@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1] +@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] @------------------------------------------------------------------------------ @ MUL diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 36627a3488..69a094dd68 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -161,6 +161,12 @@ # CHECK: cpsie if, #10 0xca 0x00 0x0a 0xf1 +# CHECK: msr CPSR_fc, r0 +0x00 0xf0 0x29 0xe1 + +# CHECK: msrmi CPSR_c, #4043309056 +0xf1 0xf4 0x21 0x43 + # CHECK: rsbs r6, r7, r8 0x08 0x60 0x77 0xe0 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index 06aa8f756d..fc7eda537a 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -744,21 +744,65 @@ # MSR #------------------------------------------------------------------------------ +# CHECK: msr CPSR_fc, #5 +# CHECK: msr APSR_g, #5 +# CHECK: msr APSR_nzcvq, #5 +# CHECK: msr APSR_nzcvq, #5 +# CHECK: msr APSR_nzcvqg, #5 +# CHECK: msr CPSR_fc, #5 # CHECK: msr CPSR_c, #5 # CHECK: msr CPSR_x, #5 -# CHECK: msr CPSR_xc, #5 - +# CHECK: msr CPSR_fc, #5 +# CHECK: msr CPSR_fc, #5 +# CHECK: msr CPSR_fsx, #5 +# CHECK: msr SPSR_fc, #5 +# CHECK: msr SPSR_fsxc, #5 +# CHECK: msr CPSR_fsxc, #5 + +0x05 0xf0 0x29 0xe3 0x05 0xf0 0x24 0xe3 0x05 0xf0 0x28 0xe3 +0x05 0xf0 0x28 0xe3 0x05 0xf0 0x2c 0xe3 - +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x21 0xe3 +0x05 0xf0 0x22 0xe3 +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x2e 0xe3 +0x05 0xf0 0x69 0xe3 +0x05 0xf0 0x6f 0xe3 +0x05 0xf0 0x2f 0xe3 + +# CHECK: msr CPSR_fc, r0 +# CHECK: msr APSR_g, r0 +# CHECK: msr APSR_nzcvq, r0 +# CHECK: msr APSR_nzcvq, r0 +# CHECK: msr APSR_nzcvqg, r0 +# CHECK: msr CPSR_fc, r0 # CHECK: msr CPSR_c, r0 # CHECK: msr CPSR_x, r0 -# CHECK: msr CPSR_xc, r0 - +# CHECK: msr CPSR_fc, r0 +# CHECK: msr CPSR_fc, r0 +# CHECK: msr CPSR_fsx, r0 +# CHECK: msr SPSR_fc, r0 +# CHECK: msr SPSR_fsxc, r0 +# CHECK: msr CPSR_fsxc, r0 + +0x00 0xf0 0x29 0xe1 0x00 0xf0 0x24 0xe1 0x00 0xf0 0x28 0xe1 +0x00 0xf0 0x28 0xe1 0x00 0xf0 0x2c 0xe1 +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x21 0xe1 +0x00 0xf0 0x22 0xe1 +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x2e 0xe1 +0x00 0xf0 0x69 0xe1 +0x00 0xf0 0x6f 0xe1 +0x00 0xf0 0x2f 0xe1 #------------------------------------------------------------------------------ # MUL |