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| author | Mihai Popa <mihail.popa@gmail.com> | 2013-06-05 13:23:51 +0000 |
|---|---|---|
| committer | Mihai Popa <mihail.popa@gmail.com> | 2013-06-05 13:23:51 +0000 |
| commit | 2248cf590617cbe91eeb6a845ad06d675d9f2e91 (patch) | |
| tree | 2032b4f5e9451f3d7b2e511c0d61e2f69c4008b4 /test | |
| parent | 7e129466d8bf25d7e0a65a4087a30a4c07746018 (diff) | |
| download | llvm-2248cf590617cbe91eeb6a845ad06d675d9f2e91.tar.gz llvm-2248cf590617cbe91eeb6a845ad06d675d9f2e91.tar.bz2 llvm-2248cf590617cbe91eeb6a845ad06d675d9f2e91.tar.xz | |
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 24 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/basic-arm-instructions.txt | 23 |
2 files changed, 47 insertions, 0 deletions
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 4440ebd260..4b72c14b97 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1645,6 +1645,30 @@ Lforward: @ CHECK: rsc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xe6,0xe0] @------------------------------------------------------------------------------ +@ RRX/RRXS +@------------------------------------------------------------------------------ + + rrx r0, r1 + rrx sp, pc + rrx pc, lr + rrx lr, sp + +@ CHECK: rrx r0, r1 @ encoding: [0x61,0x00,0xa0,0xe1] +@ CHECK: rrx sp, pc @ encoding: [0x6f,0xd0,0xa0,0xe1] +@ CHECK: rrx pc, lr @ encoding: [0x6e,0xf0,0xa0,0xe1] +@ CHECK: rrx lr, sp @ encoding: [0x6d,0xe0,0xa0,0xe1] + + rrxs r0, r1 + rrxs sp, pc + rrxs pc, lr + rrxs lr, sp + +@CHECK: rrxs r0, r1 @ encoding: [0x61,0x00,0xb0,0xe1] +@CHECK: rrxs sp, pc @ encoding: [0x6f,0xd0,0xb0,0xe1] +@CHECK: rrxs pc, lr @ encoding: [0x6e,0xf0,0xb0,0xe1] +@CHECK: rrxs lr, sp @ encoding: [0x6d,0xe0,0xb0,0xe1] + +@ ------------------------------------------------------------------------------ @ SADD16/SADD8 @------------------------------------------------------------------------------ sadd16 r1, r2, r3 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index c92322e8d7..92cfe6862e 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -1301,6 +1301,29 @@ 0x77 0x69 0xe6 0xe0 #------------------------------------------------------------------------------ +# RRX/RRXS +#------------------------------------------------------------------------------ +# CHECK: rrx r0, r1 +# CHECK: rrx sp, pc +# CHECK: rrx pc, lr +# CHECK: rrx lr, sp + +0x61 0x00 0xa0 0xe1 +0x6f 0xd0 0xa0 0xe1 +0x6e 0xf0 0xa0 0xe1 +0x6d 0xe0 0xa0 0xe1 + +# CHECK: rrxs r0, r1 +# CHECK: rrxs sp, pc +# CHECK: rrxs pc, lr +# CHECK: rrxs lr, sp + +0x61 0x00 0xb0 0xe1 +0x6f 0xd0 0xb0 0xe1 +0x6e 0xf0 0xb0 0xe1 +0x6d 0xe0 0xb0 0xe1 + +#------------------------------------------------------------------------------ # SADD16/SADD8 #------------------------------------------------------------------------------ # CHECK: sadd16 r1, r2, r3 |