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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 13:20:41 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 13:20:41 +0000 |
| commit | 9f30d43122dce961ae1625c2c429bf74bf292324 (patch) | |
| tree | c42c432b3e11cbc3992df9fd7b3167414e42ab3f /test | |
| parent | e8eafdb67685d4f5d52ab0dce2339c37e39cdc44 (diff) | |
| download | llvm-9f30d43122dce961ae1625c2c429bf74bf292324.tar.gz llvm-9f30d43122dce961ae1625c2c429bf74bf292324.tar.bz2 llvm-9f30d43122dce961ae1625c2c429bf74bf292324.tar.xz | |
[mips][msa] Implemented fill.d intrinsic.
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/Mips/msa/2r_vector_scalar.ll | 42 |
1 files changed, 33 insertions, 9 deletions
diff --git a/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/test/CodeGen/Mips/msa/2r_vector_scalar.ll index 1a468cf246..83d99d7174 100644 --- a/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -17,9 +17,9 @@ entry: declare <16 x i8> @llvm.mips.fill.b(i32) nounwind ; CHECK: llvm_mips_fill_b_test: -; CHECK: lw -; CHECK: fill.b -; CHECK: st.b +; CHECK-DAG: lw [[R1:\$[0-9]+]], +; CHECK-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]] +; CHECK-DAG: st.b [[R2]], ; CHECK: .size llvm_mips_fill_b_test ; @llvm_mips_fill_h_ARG1 = global i32 23, align 16 @@ -36,9 +36,9 @@ entry: declare <8 x i16> @llvm.mips.fill.h(i32) nounwind ; CHECK: llvm_mips_fill_h_test: -; CHECK: lw -; CHECK: fill.h -; CHECK: st.h +; CHECK-DAG: lw [[R1:\$[0-9]+]], +; CHECK-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]] +; CHECK-DAG: st.h [[R2]], ; CHECK: .size llvm_mips_fill_h_test ; @llvm_mips_fill_w_ARG1 = global i32 23, align 16 @@ -55,8 +55,32 @@ entry: declare <4 x i32> @llvm.mips.fill.w(i32) nounwind ; CHECK: llvm_mips_fill_w_test: -; CHECK: lw -; CHECK: fill.w -; CHECK: st.w +; CHECK-DAG: lw [[R1:\$[0-9]+]], +; CHECK-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]] +; CHECK-DAG: st.w [[R2]], ; CHECK: .size llvm_mips_fill_w_test ; +@llvm_mips_fill_d_ARG1 = global i64 23, align 16 +@llvm_mips_fill_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 + +define void @llvm_mips_fill_d_test() nounwind { +entry: + %0 = load i64* @llvm_mips_fill_d_ARG1 + %1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0) + store <2 x i64> %1, <2 x i64>* @llvm_mips_fill_d_RES + ret void +} + +declare <2 x i64> @llvm.mips.fill.d(i64) nounwind + +; CHECK: llvm_mips_fill_d_test: +; CHECK-DAG: lw [[R1:\$[0-9]+]], 0( +; CHECK-DAG: lw [[R2:\$[0-9]+]], 4( +; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 0 +; CHECK-DAG: insert.w [[R3]][0], [[R1]] +; CHECK-DAG: insert.w [[R3]][1], [[R2]] +; CHECK-DAG: insert.w [[R3]][2], [[R1]] +; CHECK-DAG: insert.w [[R3]][3], [[R2]] +; CHECK-DAG: st.w [[R3]], +; CHECK: .size llvm_mips_fill_d_test +; |