[SystemZ] Add STOC and STOCG

These instructions are allowed to trap even if the condition is false,
so for now they are only used for "*ptr = (cond ? x : *ptr)"-style
constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187111 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 538 insertions, 2 deletions

diff --git a/test/CodeGen/SystemZ/cond-store-03.ll b/test/CodeGen/SystemZ/cond-store-03.ll
index ba076b0acd..e2aeecfd57 100644
--- a/test/CodeGen/SystemZ/cond-store-03.ll
+++ b/test/CodeGen/SystemZ/cond-store-03.ll
@@ -1,6 +1,6 @@
 ; Test 32-bit conditional stores that are presented as selects.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 declare void @foo(i32 *)
 
diff --git a/test/CodeGen/SystemZ/cond-store-04.ll b/test/CodeGen/SystemZ/cond-store-04.ll
index f00c94cb42..1830f27ebd 100644
--- a/test/CodeGen/SystemZ/cond-store-04.ll
+++ b/test/CodeGen/SystemZ/cond-store-04.ll
@@ -1,6 +1,6 @@
 ; Test 64-bit conditional stores that are presented as selects.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 declare void @foo(i64 *)
 
diff --git a/test/CodeGen/SystemZ/cond-store-07.ll b/test/CodeGen/SystemZ/cond-store-07.ll
new file mode 100644
index 0000000000..291360b96a
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-07.ll
@@ -0,0 +1,186 @@
+; Test STOCs that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare void @foo(i32 *)
+
+; Test the simple case, with the loaded value first.
+define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK: clfi %r4, 42
+; CHECK: stocnl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK: clfi %r4, 42
+; CHECK: stocl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %alt, i32 %orig
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly sign-extended to 64 bits, with the
+; loaded value first.
+define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: clfi %r4, 42
+; CHECK: stocnl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = sext i32 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: clfi %r4, 42
+; CHECK: stocl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = sext i32 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly zero-extended to 32 bits, with the
+; loaded value first.
+define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK: clfi %r4, 42
+; CHECK: stocnl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = zext i32 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK: clfi %r4, 42
+; CHECK: stocl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = zext i32 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STOC range.
+define void @f7(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK: clfi %r4, 42
+; CHECK: stocnl %r3, 524284(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 131071
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the next word up.  Other sequences besides this one would be OK.
+define void @f8(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f8:
+; CHECK: agfi %r2, 524288
+; CHECK: clfi %r4, 42
+; CHECK: stocnl %r3, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 131072
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the low end of the STOC range.
+define void @f9(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f9:
+; CHECK: clfi %r4, 42
+; CHECK: stocnl %r3, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 -131072
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the next word down, with the same comments as f8.
+define void @f10(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f10:
+; CHECK: agfi %r2, -524292
+; CHECK: clfi %r4, 42
+; CHECK: stocnl %r3, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 -131073
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Try a frame index base.
+define void @f11(i32 %alt, i32 %limit) {
+; CHECK-LABEL: f11:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: stocnl {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i32
+  call void @foo(i32 *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  call void @foo(i32 *%ptr)
+  ret void
+}
+
+; Test that conditionally-executed stores do not use STOC, since STOC
+; is allowed to trap even when the condition is false.
+define void @f12(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f12:
+; CHECK-NOT: stoc
+; CHECK: br %r14
+entry:
+  %cmp = icmp ule i32 %a, %b
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/cond-store-08.ll b/test/CodeGen/SystemZ/cond-store-08.ll
new file mode 100644
index 0000000000..d67281c5af
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-08.ll
@@ -0,0 +1,124 @@
+; Test STOCGs that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare void @foo(i64 *)
+
+; Test with the loaded value first.
+define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK: clfi %r4, 42
+; CHECK: stocgnl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK: clfi %r4, 42
+; CHECK: stocgl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %alt, i64 %orig
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STOCG range.
+define void @f3(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: clfi %r4, 42
+; CHECK: stocgnl %r3, 524280(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 65535
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the next doubleword up.  Other sequences besides this one would be OK.
+define void @f4(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: agfi %r2, 524288
+; CHECK: clfi %r4, 42
+; CHECK: stocgnl %r3, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 65536
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the low end of the STOCG range.
+define void @f5(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK: clfi %r4, 42
+; CHECK: stocgnl %r3, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 -65536
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the next doubleword down, with the same comments as f4.
+define void @f6(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK: agfi %r2, -524296
+; CHECK: clfi %r4, 42
+; CHECK: stocgnl %r3, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 -65537
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Try a frame index base.
+define void @f7(i64 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: stocgnl {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i64
+  call void @foo(i64 *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  call void @foo(i64 *%ptr)
+  ret void
+}
+
+; Test that conditionally-executed stores do not use STOC, since STOC
+; is allowed to trap even when the condition is false.
+define void @f8(i64 %a, i64 %b, i64 *%dest) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: stocg %r3, 0(%r4)
+; CHECK: br %r14
+entry:
+  %cmp = icmp ule i64 %a, %b
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i64 %b, i64 *%dest
+  br label %exit
+
+exit:
+  ret void
+}
diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt
index 29ff69e52c..7728a516e7 100644
--- a/test/MC/Disassembler/SystemZ/insns.txt
+++ b/test/MC/Disassembler/SystemZ/insns.txt
@@ -6106,6 +6106,102 @@
 # CHECK: st %r15, 0
 0x50 0xf0 0x00 0x00
 
+# CHECK: stoc %r1, 2(%r3), 0
+0xeb 0x10 0x30 0x02 0x00 0xf3
+
+# CHECK: stoco %r1, 2(%r3)
+0xeb 0x11 0x30 0x02 0x00 0xf3
+
+# CHECK: stoch %r1, 2(%r3)
+0xeb 0x12 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnle %r1, 2(%r3)
+0xeb 0x13 0x30 0x02 0x00 0xf3
+
+# CHECK: stocl %r1, 2(%r3)
+0xeb 0x14 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnhe %r1, 2(%r3)
+0xeb 0x15 0x30 0x02 0x00 0xf3
+
+# CHECK: stoclh %r1, 2(%r3)
+0xeb 0x16 0x30 0x02 0x00 0xf3
+
+# CHECK: stocne %r1, 2(%r3)
+0xeb 0x17 0x30 0x02 0x00 0xf3
+
+# CHECK: stoce %r1, 2(%r3)
+0xeb 0x18 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnlh %r1, 2(%r3)
+0xeb 0x19 0x30 0x02 0x00 0xf3
+
+# CHECK: stoche %r1, 2(%r3)
+0xeb 0x1a 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnl %r1, 2(%r3)
+0xeb 0x1b 0x30 0x02 0x00 0xf3
+
+# CHECK: stocle %r1, 2(%r3)
+0xeb 0x1c 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnh %r1, 2(%r3)
+0xeb 0x1d 0x30 0x02 0x00 0xf3
+
+# CHECK: stocno %r1, 2(%r3)
+0xeb 0x1e 0x30 0x02 0x00 0xf3
+
+# CHECK: stoc %r1, 2(%r3), 15
+0xeb 0x1f 0x30 0x02 0x00 0xf3
+
+# CHECK: stocg %r1, 2(%r3), 0
+0xeb 0x10 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgo %r1, 2(%r3)
+0xeb 0x11 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgh %r1, 2(%r3)
+0xeb 0x12 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnle %r1, 2(%r3)
+0xeb 0x13 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgl %r1, 2(%r3)
+0xeb 0x14 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnhe %r1, 2(%r3)
+0xeb 0x15 0x30 0x02 0x00 0xe3
+
+# CHECK: stocglh %r1, 2(%r3)
+0xeb 0x16 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgne %r1, 2(%r3)
+0xeb 0x17 0x30 0x02 0x00 0xe3
+
+# CHECK: stocge %r1, 2(%r3)
+0xeb 0x18 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnlh %r1, 2(%r3)
+0xeb 0x19 0x30 0x02 0x00 0xe3
+
+# CHECK: stocghe %r1, 2(%r3)
+0xeb 0x1a 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnl %r1, 2(%r3)
+0xeb 0x1b 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgle %r1, 2(%r3)
+0xeb 0x1c 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnh %r1, 2(%r3)
+0xeb 0x1d 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgno %r1, 2(%r3)
+0xeb 0x1e 0x30 0x02 0x00 0xe3
+
+# CHECK: stocg %r1, 2(%r3), 15
+0xeb 0x1f 0x30 0x02 0x00 0xe3
+
 # CHECK: s %r0, 0
 0x5b 0x00 0x00 0x00
 
diff --git a/test/MC/SystemZ/insn-bad-z196.s b/test/MC/SystemZ/insn-bad-z196.s
index b4dc529531..f62ea74fa0 100644
--- a/test/MC/SystemZ/insn-bad-z196.s
+++ b/test/MC/SystemZ/insn-bad-z196.s
@@ -65,3 +65,37 @@
 	srlk	%r0,%r0,524288
 	srlk	%r0,%r0,0(%r0)
 	srlk	%r0,%r0,0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: stoc	%r0,0,-1
+#CHECK: error: invalid operand
+#CHECK: stoc	%r0,0,16
+#CHECK: error: invalid operand
+#CHECK: stoc	%r0,-524289,1
+#CHECK: error: invalid operand
+#CHECK: stoc	%r0,524288,1
+#CHECK: error: invalid use of indexed addressing
+#CHECK: stoc	%r0,0(%r1,%r2),1
+
+	stoc	%r0,0,-1
+	stoc	%r0,0,16
+	stoc	%r0,-524289,1
+	stoc	%r0,524288,1
+	stoc	%r0,0(%r1,%r2),1
+
+#CHECK: error: invalid operand
+#CHECK: stocg	%r0,0,-1
+#CHECK: error: invalid operand
+#CHECK: stocg	%r0,0,16
+#CHECK: error: invalid operand
+#CHECK: stocg	%r0,-524289,1
+#CHECK: error: invalid operand
+#CHECK: stocg	%r0,524288,1
+#CHECK: error: invalid use of indexed addressing
+#CHECK: stocg	%r0,0(%r1,%r2),1
+
+	stocg	%r0,0,-1
+	stocg	%r0,0,16
+	stocg	%r0,-524289,1
+	stocg	%r0,524288,1
+	stocg	%r0,0(%r1,%r2),1
diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s
index 422c689e93..5b0ed59cb1 100644
--- a/test/MC/SystemZ/insn-good-z196.s
+++ b/test/MC/SystemZ/insn-good-z196.s
@@ -295,6 +295,102 @@
 	srlk	%r0,%r0,524287(%r1)
 	srlk	%r0,%r0,524287(%r15)
 
+#CHECK: stoc	%r0, 0, 0               # encoding: [0xeb,0x00,0x00,0x00,0x00,0xf3]
+#CHECK: stoc	%r0, 0, 15              # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xf3]
+#CHECK: stoc	%r0, -524288, 0         # encoding: [0xeb,0x00,0x00,0x00,0x80,0xf3]
+#CHECK: stoc	%r0, 524287, 0          # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xf3]
+#CHECK: stoc	%r0, 0(%r1), 0          # encoding: [0xeb,0x00,0x10,0x00,0x00,0xf3]
+#CHECK: stoc	%r0, 0(%r15), 0         # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xf3]
+#CHECK: stoc	%r15, 0, 0              # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xf3]
+#CHECK: stoc	%r1, 4095(%r2), 3       # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xf3]
+
+	stoc	%r0,0,0
+	stoc	%r0,0,15
+	stoc	%r0,-524288,0
+	stoc	%r0,524287,0
+	stoc	%r0,0(%r1),0
+	stoc	%r0,0(%r15),0
+	stoc	%r15,0,0
+	stoc	%r1,4095(%r2),3
+
+#CHECK: stoco   %r1, 2(%r3)             # encoding: [0xeb,0x11,0x30,0x02,0x00,0xf3]
+#CHECK: stoch   %r1, 2(%r3)             # encoding: [0xeb,0x12,0x30,0x02,0x00,0xf3]
+#CHECK: stocnle %r1, 2(%r3)             # encoding: [0xeb,0x13,0x30,0x02,0x00,0xf3]
+#CHECK: stocl   %r1, 2(%r3)             # encoding: [0xeb,0x14,0x30,0x02,0x00,0xf3]
+#CHECK: stocnhe %r1, 2(%r3)             # encoding: [0xeb,0x15,0x30,0x02,0x00,0xf3]
+#CHECK: stoclh  %r1, 2(%r3)             # encoding: [0xeb,0x16,0x30,0x02,0x00,0xf3]
+#CHECK: stocne  %r1, 2(%r3)             # encoding: [0xeb,0x17,0x30,0x02,0x00,0xf3]
+#CHECK: stoce   %r1, 2(%r3)             # encoding: [0xeb,0x18,0x30,0x02,0x00,0xf3]
+#CHECK: stocnlh %r1, 2(%r3)             # encoding: [0xeb,0x19,0x30,0x02,0x00,0xf3]
+#CHECK: stoche  %r1, 2(%r3)             # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xf3]
+#CHECK: stocnl  %r1, 2(%r3)             # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xf3]
+#CHECK: stocle  %r1, 2(%r3)             # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xf3]
+#CHECK: stocnh  %r1, 2(%r3)             # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xf3]
+#CHECK: stocno  %r1, 2(%r3)             # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xf3]
+
+	stoco   %r1,2(%r3)
+	stoch   %r1,2(%r3)
+	stocnle %r1,2(%r3)
+	stocl   %r1,2(%r3)
+	stocnhe %r1,2(%r3)
+	stoclh  %r1,2(%r3)
+	stocne  %r1,2(%r3)
+	stoce   %r1,2(%r3)
+	stocnlh %r1,2(%r3)
+	stoche  %r1,2(%r3)
+	stocnl  %r1,2(%r3)
+	stocle  %r1,2(%r3)
+	stocnh  %r1,2(%r3)
+	stocno  %r1,2(%r3)
+
+#CHECK: stocg	%r0, 0, 0               # encoding: [0xeb,0x00,0x00,0x00,0x00,0xe3]
+#CHECK: stocg	%r0, 0, 15              # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xe3]
+#CHECK: stocg	%r0, -524288, 0         # encoding: [0xeb,0x00,0x00,0x00,0x80,0xe3]
+#CHECK: stocg	%r0, 524287, 0          # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xe3]
+#CHECK: stocg	%r0, 0(%r1), 0          # encoding: [0xeb,0x00,0x10,0x00,0x00,0xe3]
+#CHECK: stocg	%r0, 0(%r15), 0         # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xe3]
+#CHECK: stocg	%r15, 0, 0              # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xe3]
+#CHECK: stocg	%r1, 4095(%r2), 3       # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xe3]
+
+	stocg	%r0,0,0
+	stocg	%r0,0,15
+	stocg	%r0,-524288,0
+	stocg	%r0,524287,0
+	stocg	%r0,0(%r1),0
+	stocg	%r0,0(%r15),0
+	stocg	%r15,0,0
+	stocg	%r1,4095(%r2),3
+
+#CHECK: stocgo   %r1, 2(%r3)            # encoding: [0xeb,0x11,0x30,0x02,0x00,0xe3]
+#CHECK: stocgh   %r1, 2(%r3)            # encoding: [0xeb,0x12,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnle %r1, 2(%r3)            # encoding: [0xeb,0x13,0x30,0x02,0x00,0xe3]
+#CHECK: stocgl   %r1, 2(%r3)            # encoding: [0xeb,0x14,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnhe %r1, 2(%r3)            # encoding: [0xeb,0x15,0x30,0x02,0x00,0xe3]
+#CHECK: stocglh  %r1, 2(%r3)            # encoding: [0xeb,0x16,0x30,0x02,0x00,0xe3]
+#CHECK: stocgne  %r1, 2(%r3)            # encoding: [0xeb,0x17,0x30,0x02,0x00,0xe3]
+#CHECK: stocge   %r1, 2(%r3)            # encoding: [0xeb,0x18,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnlh %r1, 2(%r3)            # encoding: [0xeb,0x19,0x30,0x02,0x00,0xe3]
+#CHECK: stocghe  %r1, 2(%r3)            # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnl  %r1, 2(%r3)            # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xe3]
+#CHECK: stocgle  %r1, 2(%r3)            # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnh  %r1, 2(%r3)            # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xe3]
+#CHECK: stocgno  %r1, 2(%r3)            # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xe3]
+
+	stocgo   %r1,2(%r3)
+	stocgh   %r1,2(%r3)
+	stocgnle %r1,2(%r3)
+	stocgl   %r1,2(%r3)
+	stocgnhe %r1,2(%r3)
+	stocglh  %r1,2(%r3)
+	stocgne  %r1,2(%r3)
+	stocge   %r1,2(%r3)
+	stocgnlh %r1,2(%r3)
+	stocghe  %r1,2(%r3)
+	stocgnl  %r1,2(%r3)
+	stocgle  %r1,2(%r3)
+	stocgnh  %r1,2(%r3)
+	stocgno  %r1,2(%r3)
+
 #CHECK: xgrk	%r0, %r0, %r0           # encoding: [0xb9,0xe7,0x00,0x00]
 #CHECK: xgrk	%r0, %r0, %r15          # encoding: [0xb9,0xe7,0xf0,0x00]
 #CHECK: xgrk	%r0, %r15, %r0          # encoding: [0xb9,0xe7,0x00,0x0f]