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| author | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-27 13:28:17 +0000 |
|---|---|---|
| committer | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-27 13:28:17 +0000 |
| commit | cca114611945332852094fcadfaa4ffbd012bfb3 (patch) | |
| tree | 96aeb92bfbe577c6bd513fcfa69877be972c913a /test | |
| parent | 9f30d43122dce961ae1625c2c429bf74bf292324 (diff) | |
| download | llvm-cca114611945332852094fcadfaa4ffbd012bfb3.tar.gz llvm-cca114611945332852094fcadfaa4ffbd012bfb3.tar.bz2 llvm-cca114611945332852094fcadfaa4ffbd012bfb3.tar.xz | |
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:
LDRD<c> <Rt>, <Rt2>, ...
(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)
If those two constraints are not met the result of executing the instruction will be unpredictable.
Constraint (b) was already enforced, this commit adds support for constraint (a).
Fixes rdar://14479793.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/arm-ldrd.s | 20 | ||||
| -rw-r--r-- | test/MC/ARM/arm-memory-instructions.s | 40 |
2 files changed, 40 insertions, 20 deletions
diff --git a/test/MC/ARM/arm-ldrd.s b/test/MC/ARM/arm-ldrd.s new file mode 100644 index 0000000000..8522d26a97 --- /dev/null +++ b/test/MC/ARM/arm-ldrd.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -arch arm -mattr=+v5te \ +// RUN: < %s >/dev/null 2> %t +// RUN: grep "error: Rt must be even-numbered" %t | count 7 +// RUN: grep "error: Rt can't be R14" %t | count 7 +// rdar://14479793 + +ldrd r1, r2, [pc, #0] +ldrd lr, pc, [pc, #0] +ldrd r1, r2, [r3, #4] +ldrd lr, pc, [r3, #4] +ldrd r1, r2, [r3], #4 +ldrd lr, pc, [r3], #4 +ldrd r1, r2, [r3, #4]! +ldrd lr, pc, [r3, #4]! +ldrd r1, r2, [r3, -r4]! +ldrd lr, pc, [r3, -r4]! +ldrd r1, r2, [r3, r4] +ldrd lr, pc, [r3, r4] +ldrd r1, r2, [r3], r4 +ldrd lr, pc, [r3], r4 diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s index e9f0c3da7c..ad35dd26a0 100644 --- a/test/MC/ARM/arm-memory-instructions.s +++ b/test/MC/ARM/arm-memory-instructions.s @@ -114,21 +114,21 @@ _func: @------------------------------------------------------------------------------ @ LDRD (immediate) @------------------------------------------------------------------------------ - ldrd r3, r4, [r5] - ldrd r7, r8, [r2, #15] - ldrd r1, r2, [r9, #32]! + ldrd r2, r3, [r5] + ldrd r6, r7, [r2, #15] + ldrd r0, r1, [r9, #32]! ldrd r6, r7, [r1], #8 - ldrd r1, r2, [r8], #0 - ldrd r1, r2, [r8], #+0 - ldrd r1, r2, [r8], #-0 + ldrd r0, r1, [r8], #0 + ldrd r0, r1, [r8], #+0 + ldrd r0, r1, [r8], #-0 -@ CHECK: ldrd r3, r4, [r5] @ encoding: [0xd0,0x30,0xc5,0xe1] -@ CHECK: ldrd r7, r8, [r2, #15] @ encoding: [0xdf,0x70,0xc2,0xe1] -@ CHECK: ldrd r1, r2, [r9, #32]! @ encoding: [0xd0,0x12,0xe9,0xe1] -@ CHECK: ldrd r6, r7, [r1], #8 @ encoding: [0xd8,0x60,0xc1,0xe0] -@ CHECK: ldrd r1, r2, [r8], #0 @ encoding: [0xd0,0x10,0xc8,0xe0] -@ CHECK: ldrd r1, r2, [r8], #0 @ encoding: [0xd0,0x10,0xc8,0xe0] -@ CHECK: ldrd r1, r2, [r8], #-0 @ encoding: [0xd0,0x10,0x48,0xe0] +@ CHECK: ldrd r2, r3, [r5] @ encoding: [0xd0,0x20,0xc5,0xe1] +@ CHECK: ldrd r6, r7, [r2, #15] @ encoding: [0xdf,0x60,0xc2,0xe1] +@ CHECK: ldrd r0, r1, [r9, #32]! @ encoding: [0xd0,0x02,0xe9,0xe1] +@ CHECK: ldrd r6, r7, [r1], #8 @ encoding: [0xd8,0x60,0xc1,0xe0] +@ CHECK: ldrd r0, r1, [r8], #0 @ encoding: [0xd0,0x00,0xc8,0xe0] +@ CHECK: ldrd r0, r1, [r8], #0 @ encoding: [0xd0,0x00,0xc8,0xe0] +@ CHECK: ldrd r0, r1, [r8], #-0 @ encoding: [0xd0,0x00,0x48,0xe0] @------------------------------------------------------------------------------ @@ -143,15 +143,15 @@ Lbaz: .quad 0 @------------------------------------------------------------------------------ @ LDRD (register) @------------------------------------------------------------------------------ - ldrd r3, r4, [r1, r3] + ldrd r4, r5, [r1, r3] ldrd r4, r5, [r7, r2]! - ldrd r1, r2, [r8], r12 - ldrd r1, r2, [r8], -r12 + ldrd r0, r1, [r8], r12 + ldrd r0, r1, [r8], -r12 -@ CHECK: ldrd r3, r4, [r1, r3] @ encoding: [0xd3,0x30,0x81,0xe1] -@ CHECK: ldrd r4, r5, [r7, r2]! @ encoding: [0xd2,0x40,0xa7,0xe1] -@ CHECK: ldrd r1, r2, [r8], r12 @ encoding: [0xdc,0x10,0x88,0xe0] -@ CHECK: ldrd r1, r2, [r8], -r12 @ encoding: [0xdc,0x10,0x08,0xe0] +@ CHECK: ldrd r4, r5, [r1, r3] @ encoding: [0xd3,0x40,0x81,0xe1] +@ CHECK: ldrd r4, r5, [r7, r2]! @ encoding: [0xd2,0x40,0xa7,0xe1] +@ CHECK: ldrd r0, r1, [r8], r12 @ encoding: [0xdc,0x00,0x88,0xe0] +@ CHECK: ldrd r0, r1, [r8], -r12 @ encoding: [0xdc,0x00,0x08,0xe0] @------------------------------------------------------------------------------ |