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author | Jim Grosbach <grosbach@apple.com> | 2011-10-28 16:43:40 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2011-10-28 16:43:40 +0000 |
commit | be5d6bcfc6ad4d5b771bb491c8ec6c87fcd3c425 (patch) | |
tree | 54a86f4d9fbb5d00b132d9b66def34e7e0ee45b0 /utils/TableGen | |
parent | 398daae4cc0182f77ff0e68d7ba4b7614ce8af71 (diff) | |
download | llvm-be5d6bcfc6ad4d5b771bb491c8ec6c87fcd3c425.tar.gz llvm-be5d6bcfc6ad4d5b771bb491c8ec6c87fcd3c425.tar.bz2 llvm-be5d6bcfc6ad4d5b771bb491c8ec6c87fcd3c425.tar.xz |
Allow register classes to match a containing class in InstAliases.
If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143200 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
-rw-r--r-- | utils/TableGen/CodeGenInstruction.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp index 53d499f395..9822de819d 100644 --- a/utils/TableGen/CodeGenInstruction.cpp +++ b/utils/TableGen/CodeGenInstruction.cpp @@ -423,6 +423,15 @@ bool CodeGenInstAlias::tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo, return true; } + // For register operands, the source register class can be a subclass + // of the instruction register class, not just an exact match. + if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) { + if (!InstOpRec->isSubClassOf("RegisterClass")) + return false; + return T.getRegisterClass(InstOpRec) + .hasSubClass(&T.getRegisterClass(ADI->getDef())); + } + // Handle explicit registers. if (ADI && ADI->getDef()->isSubClassOf("Register")) { if (InstOpRec->isSubClassOf("OptionalDefOperand")) { |