diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 14 | ||||
| -rw-r--r-- | test/CodeGen/X86/bmi.ll | 18 |
2 files changed, 32 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 306fb7e199..d867414a98 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -18503,6 +18503,20 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, } } // BEXTR + // Check for BZHI with contiguous mask: (and X, 0x0..0f..f) + // This should be checked after BEXTR - when X is a shift, a BEXTR is + // preferrable. + if (Subtarget->hasBMI2()) { + if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { + uint64_t Mask = C->getZExtValue(); + if (isMask_64(Mask)) { + unsigned LZ = CountTrailingOnes_64(Mask); + return DAG.getNode(X86ISD::BZHI, DL, VT, N0, + DAG.getConstant(LZ, MVT::i8)); + } + } + } + return SDValue(); } diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll index 242075a878..1dc2edb7ea 100644 --- a/test/CodeGen/X86/bmi.ll +++ b/test/CodeGen/X86/bmi.ll @@ -216,6 +216,24 @@ entry: ; CHECK: bzhiq } +define i32 @bzhi32_constant_mask(i32 %x) #0 { +entry: + %and = and i32 %x, 1073741823 + ret i32 %and +; CHECK-LABEL: bzhi32_constant_mask: +; CHECK: movb $30, %al +; CHECK: bzhil %eax, %edi, %eax +} + +define i64 @bzhi64_constant_mask(i64 %x) #0 { +entry: + %and = and i64 %x, 4611686018427387903 + ret i64 %and +; CHECK-LABEL: bzhi64_constant_mask: +; CHECK: movb $62, %al +; CHECK: bzhiq %rax, %rdi, %rax +} + define i32 @blsi32(i32 %x) nounwind readnone { %tmp = sub i32 0, %x %tmp2 = and i32 %x, %tmp |