diff options
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 8681844005..eae19b9539 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -18,7 +18,7 @@ #define DEBUG_TYPE "pre-RA-sched" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" @@ -106,8 +106,8 @@ private: void ScheduleDAGRRList::Schedule() { DOUT << "********** List Scheduling **********\n"; - LiveRegDefs.resize(MRI->getNumRegs(), NULL); - LiveRegCycles.resize(MRI->getNumRegs(), 0); + LiveRegDefs.resize(TRI->getNumRegs(), NULL); + LiveRegCycles.resize(TRI->getNumRegs(), 0); // Build scheduling units. BuildSchedUnits(); @@ -651,7 +651,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, if (RegAdded.insert(Reg)) LRegs.push_back(Reg); } - for (const unsigned *Alias = MRI->getAliasSet(Reg); + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) { if (RegAdded.insert(*Alias)) @@ -672,7 +672,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, if (RegAdded.insert(*Reg)) LRegs.push_back(*Reg); } - for (const unsigned *Alias = MRI->getAliasSet(*Reg); + for (const unsigned *Alias = TRI->getAliasSet(*Reg); *Alias; ++Alias) if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) { if (RegAdded.insert(*Alias)) @@ -768,8 +768,8 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { // Issue expensive cross register class copies. MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); const TargetRegisterClass *RC = - MRI->getPhysicalRegisterRegClass(VT, Reg); - const TargetRegisterClass *DestRC = MRI->getCrossCopyRegClass(RC); + TRI->getPhysicalRegisterRegClass(VT, Reg); + const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); if (!DestRC) { assert(false && "Don't know how to copy this physical register!"); abort(); @@ -1063,11 +1063,11 @@ namespace { std::vector<unsigned> SethiUllmanNumbers; const TargetInstrInfo *TII; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; public: explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii, - const MRegisterInfo *mri) - : TII(tii), MRI(mri) {} + const TargetRegisterInfo *tri) + : TII(tii), TRI(tri) {} void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap, std::vector<SUnit> &sunits) { @@ -1320,7 +1320,7 @@ static bool hasCopyToRegUse(SUnit *SU) { /// physical register def. static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, const TargetInstrInfo *TII, - const MRegisterInfo *MRI) { + const TargetRegisterInfo *TRI) { SDNode *N = SuccSU->Node; unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs(); const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs(); @@ -1337,7 +1337,7 @@ static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, unsigned Reg = ImpDefs[i - NumDefs]; for (;*SUImpDefs; ++SUImpDefs) { unsigned SUReg = *SUImpDefs; - if (MRI->regsOverlap(Reg, SUReg)) + if (TRI->regsOverlap(Reg, SUReg)) return true; } } @@ -1388,7 +1388,7 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() { // Don't constrain nodes with physical register defs if the // predecessor can clobber them. if (SuccSU->hasPhysRegDefs) { - if (canClobberPhysRegDefs(SuccSU, SU, TII, MRI)) + if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) continue; } // Don't constraint extract_subreg / insert_subreg these may be @@ -1580,9 +1580,9 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, MachineBasicBlock *BB) { const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo(); - const MRegisterInfo *MRI = DAG->getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo(); return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, - new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, MRI)); + new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, TRI)); } llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, |