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-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp8
1 files changed, 0 insertions, 8 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index cf11c97f98..650aaae7df 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3012,14 +3012,6 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
case ISD::AND:
case ISD::OR:
case ISD::XOR:
- // The input may have strange things in the top bits of the registers, but
- // these operations don't care. They may have weird bits going out, but
- // that too is okay if they are integer operations.
- Tmp1 = PromoteOp(Node->getOperand(0));
- Tmp2 = PromoteOp(Node->getOperand(1));
- assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
- break;
case ISD::ADD:
case ISD::SUB:
case ISD::MUL: