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-rw-r--r--lib/Target/ARM64/ARM64SchedCyclone.td4
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM64/ARM64SchedCyclone.td b/lib/Target/ARM64/ARM64SchedCyclone.td
index 65c68b3f05..8b3a7592af 100644
--- a/lib/Target/ARM64/ARM64SchedCyclone.td
+++ b/lib/Target/ARM64/ARM64SchedCyclone.td
@@ -342,7 +342,9 @@ def : InstRW<[WriteVMov], (instrs ORRv16i8)>;
// INS V[x],V[y] is a WriteV.
// FMOVWSr,FMOVXDr,FMOVXDHighr
-def : SchedAlias<WriteFCopy, WriteVLD>;
+def : WriteRes<WriteFCopy, [CyUnitLS]> {
+ let Latency = 5;
+}
// FMOVSWr,FMOVDXr
def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>;