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| author | Chad Rosier <mcrosier@codeaurora.org> | 2014-04-18 21:22:04 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2014-04-18 21:22:04 +0000 |
| commit | 6c4ec69c6be8b0003b420b58df585caa0563ef70 (patch) | |
| tree | 218f64492fbff02fa2c8fea3f34940f01f2dc069 /lib/Target/ARM64/ARM64SchedCyclone.td | |
| parent | ed5604850a0dbb79dd41a8d950b776e553992fa3 (diff) | |
| download | llvm-6c4ec69c6be8b0003b420b58df585caa0563ef70.tar.gz llvm-6c4ec69c6be8b0003b420b58df585caa0563ef70.tar.bz2 llvm-6c4ec69c6be8b0003b420b58df585caa0563ef70.tar.xz | |
[ARM64] Ports the Cortex-A53 Machine Model description from AArch64.
Summary:
This port includes the rudimentary latencies that were provided for
the Cortex-A53 Machine Model in the AArch64 backend. It also changes
the SchedAlias for COPY in the Cyclone model to an explicit
WriteRes mapping to avoid conflicts in other subtargets.
Differential Revision: http://reviews.llvm.org/D3427
Patch by Dave Estes <cestes@codeaurora.org>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206652 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM64/ARM64SchedCyclone.td')
| -rw-r--r-- | lib/Target/ARM64/ARM64SchedCyclone.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM64/ARM64SchedCyclone.td b/lib/Target/ARM64/ARM64SchedCyclone.td index 65c68b3f05..8b3a7592af 100644 --- a/lib/Target/ARM64/ARM64SchedCyclone.td +++ b/lib/Target/ARM64/ARM64SchedCyclone.td @@ -342,7 +342,9 @@ def : InstRW<[WriteVMov], (instrs ORRv16i8)>; // INS V[x],V[y] is a WriteV. // FMOVWSr,FMOVXDr,FMOVXDHighr -def : SchedAlias<WriteFCopy, WriteVLD>; +def : WriteRes<WriteFCopy, [CyUnitLS]> { + let Latency = 5; +} // FMOVSWr,FMOVDXr def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>; |