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-rw-r--r--test/CodeGen/PowerPC/bdzlr.ll9
-rw-r--r--test/CodeGen/PowerPC/crbits.ll174
-rw-r--r--test/CodeGen/PowerPC/early-ret2.ll6
-rw-r--r--test/CodeGen/PowerPC/fold-zero.ll13
-rw-r--r--test/CodeGen/PowerPC/optcmp.ll2
-rw-r--r--test/CodeGen/PowerPC/rlwimi-and.ll2
-rw-r--r--test/CodeGen/PowerPC/sdag-ppcf128.ll2
-rw-r--r--test/CodeGen/PowerPC/setcc_no_zext.ll4
-rw-r--r--test/CodeGen/PowerPC/seteq-0.ll7
-rw-r--r--test/CodeGen/PowerPC/subsumes-pred-regs.ll2
10 files changed, 212 insertions, 9 deletions
diff --git a/test/CodeGen/PowerPC/bdzlr.ll b/test/CodeGen/PowerPC/bdzlr.ll
index e487558e94..29b74c6c8c 100644
--- a/test/CodeGen/PowerPC/bdzlr.ll
+++ b/test/CodeGen/PowerPC/bdzlr.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-CRB
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -54,6 +55,12 @@ for.end: ; preds = %for.body, %if.end,
; CHECK: bnelr
; CHECK: bdzlr
; CHECK-NOT: blr
+
+; CHECK-CRB: @lua_xmove
+; CHECK-CRB: bclr 12,
+; CHECK-CRB: bclr 12,
+; CHECK-CRB: bdzlr
+; CHECK-CRB-NOT: blr
}
attributes #0 = { nounwind }
diff --git a/test/CodeGen/PowerPC/crbits.ll b/test/CodeGen/PowerPC/crbits.ll
new file mode 100644
index 0000000000..998e940e8a
--- /dev/null
+++ b/test/CodeGen/PowerPC/crbits.ll
@@ -0,0 +1,174 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; FIXME: For a number of these we load (1, 0) for the isel into two registers,
+; whereas if we reverse the condition, we could use only one register (using ZERO
+; for 0 in the isel).
+
+; Function Attrs: nounwind readnone
+define zeroext i1 @test1(float %v1, float %v2) #0 {
+entry:
+ %cmp = fcmp oge float %v1, %v2
+ %cmp2 = fcmp ole float %v2, 0.000000e+00
+ %and5 = and i1 %cmp, %cmp2
+ ret i1 %and5
+
+; CHECK-LABEL: @test1
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: li [[REG1:[0-9]+]], 1
+; CHECK-DAG: lfs [[REG2:[0-9]+]],
+; CHECK-DAG: li [[REG3:[0-9]+]], 0
+; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
+; CHECK: crnor
+; CHECK: crnor
+; CHECK: crand [[REG4:[0-9]+]],
+; CHECK: isel 3, [[REG1]], [[REG3]], [[REG4]]
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+define zeroext i1 @test2(float %v1, float %v2) #0 {
+entry:
+ %cmp = fcmp oge float %v1, %v2
+ %cmp2 = fcmp ole float %v2, 0.000000e+00
+ %xor5 = xor i1 %cmp, %cmp2
+ ret i1 %xor5
+
+; CHECK-LABEL: @test2
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: li [[REG1:[0-9]+]], 1
+; CHECK-DAG: lfs [[REG2:[0-9]+]],
+; CHECK-DAG: li [[REG3:[0-9]+]], 0
+; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
+; CHECK: crnor
+; CHECK: crnor
+; CHECK: crxor [[REG4:[0-9]+]],
+; CHECK: isel 3, [[REG1]], [[REG3]], [[REG4]]
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
+entry:
+ %cmp = fcmp oge float %v1, %v2
+ %cmp2 = fcmp ole float %v2, 0.000000e+00
+ %cmp4 = icmp ne i32 %x, -2
+ %and7 = and i1 %cmp2, %cmp4
+ %xor8 = xor i1 %cmp, %and7
+ ret i1 %xor8
+
+; CHECK-LABEL: @test3
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: li [[REG1:[0-9]+]], 1
+; CHECK-DAG: lfs [[REG2:[0-9]+]],
+; CHECK-DAG: li [[REG3:[0-9]+]], 0
+; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
+; CHECK: crnor
+; CHECK: crnor
+; CHECK: crandc
+; CHECK: crxor [[REG4:[0-9]+]],
+; CHECK: isel 3, [[REG1]], [[REG3]], [[REG4]]
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+define zeroext i1 @test4(i1 zeroext %v1, i1 zeroext %v2, i1 zeroext %v3) #0 {
+entry:
+ %and8 = and i1 %v1, %v2
+ %or9 = or i1 %and8, %v3
+ ret i1 %or9
+
+; CHECK-DAG: @test4
+; CHECK: and [[REG1:[0-9]+]], 3, 4
+; CHECK: or 3, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
+entry:
+ %and6 = and i1 %v1, %v2
+ %cmp = icmp ne i32 %v3, -2
+ %or7 = or i1 %and6, %cmp
+ ret i1 %or7
+
+; CHECK-LABEL: @test5
+; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4
+; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
+; CHECK: li [[REG3:[0-9]+]], 1
+; CHECK: andi. {{[0-9]+}}, [[REG1]], 1
+; CHECK: li [[REG4:[0-9]+]], 0
+; CHECK: crorc [[REG5:[0-9]+]],
+; CHECK: isel 3, [[REG3]], [[REG4]], [[REG5]]
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
+entry:
+ %cmp = icmp ne i32 %v3, -2
+ %or6 = or i1 %cmp, %v2
+ %and7 = and i1 %or6, %v1
+ ret i1 %and7
+
+; CHECK-LABEL: @test6
+; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
+; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
+; CHECK-DAG: cror [[REG1:[0-9]+]], 1, 1
+; CHECK: andi. {{[0-9]+}}, 4, 1
+; CHECK: li [[REG2:[0-9]+]], 1
+; CHECK: li [[REG3:[0-9]+]], 0
+; CHECK: crorc [[REG4:[0-9]+]], 1,
+; CHECK: crand [[REG5:[0-9]+]], [[REG4]], [[REG1]]
+; CHECK: isel 3, [[REG2]], [[REG3]], [[REG5]]
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 {
+entry:
+ %cond = select i1 %v2, i32 %i1, i32 %i2
+ ret i32 %cond
+
+; CHECK-LABEL: @test7
+; CHECK: andi. {{[0-9]+}}, 3, 1
+; CHECK: isel [[REG1:[0-9]+]], 4, 5, 1
+; CHECK: extsw 3, [[REG1]]
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+define float @test8(i1 zeroext %v2, float %v1, float %v3) #0 {
+entry:
+ %cond = select i1 %v2, float %v1, float %v3
+ ret float %cond
+
+; CHECK-LABEL: @test8
+; CHECK: andi. {{[0-9]+}}, 3, 1
+; CHECK: bclr 12, 1, 0
+; CHECK: fmr 1, 2
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+define signext i32 @test10(i32 signext %v1, i32 signext %v2) #0 {
+entry:
+ %tobool = icmp ne i32 %v1, 0
+ %lnot = icmp eq i32 %v2, 0
+ %and3 = and i1 %tobool, %lnot
+ %and = zext i1 %and3 to i32
+ ret i32 %and
+
+; CHECK-LABEL: @test10
+; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
+; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
+; CHECK-DAG: li [[REG1:[0-9]+]], 0
+; CHECK-DAG: li [[REG2:[0-9]+]], 1
+; CHECK: crandc [[REG3:[0-9]+]],
+; CHECK: isel 3, [[REG2]], [[REG1]], [[REG3]]
+; CHECK: blr
+}
+
+attributes #0 = { nounwind readnone }
+
diff --git a/test/CodeGen/PowerPC/early-ret2.ll b/test/CodeGen/PowerPC/early-ret2.ll
index a274e2c265..a8e456fea6 100644
--- a/test/CodeGen/PowerPC/early-ret2.ll
+++ b/test/CodeGen/PowerPC/early-ret2.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-CRB
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -17,6 +18,9 @@ while.end: ; preds = %while.body, %while.
; CHECK: @_Z8example3iPiS_
; CHECK: bnelr
+
+; CHECK-CRB: @_Z8example3iPiS_
+; CHECK-CRB: bclr 12,
}
attributes #0 = { noinline nounwind }
diff --git a/test/CodeGen/PowerPC/fold-zero.ll b/test/CodeGen/PowerPC/fold-zero.ll
index c7ec6fade5..c1eea43017 100644
--- a/test/CodeGen/PowerPC/fold-zero.ll
+++ b/test/CodeGen/PowerPC/fold-zero.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck -check-prefix=CHECK-CRB %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -12,3 +13,13 @@ define i32 @test1(i1 %a, i32 %c) nounwind {
; CHECK: blr
}
+define i32 @test2(i1 %a, i32 %c) nounwind {
+ %x = select i1 %a, i32 0, i32 %c
+ ret i32 %x
+
+; CHECK-CRB: @test2
+; CHECK-CRB-NOT: li {{[0-9]+}}, 0
+; CHECK-CRB: isel 3, 0,
+; CHECK-CRB: blr
+}
+
diff --git a/test/CodeGen/PowerPC/optcmp.ll b/test/CodeGen/PowerPC/optcmp.ll
index 35aabfa52c..d929eae206 100644
--- a/test/CodeGen/PowerPC/optcmp.ll
+++ b/test/CodeGen/PowerPC/optcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -disable-ppc-cmp-opt=0 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
diff --git a/test/CodeGen/PowerPC/rlwimi-and.ll b/test/CodeGen/PowerPC/rlwimi-and.ll
index 7963249ddf..213363ee81 100644
--- a/test/CodeGen/PowerPC/rlwimi-and.ll
+++ b/test/CodeGen/PowerPC/rlwimi-and.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=-crbits < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-bgq-linux"
diff --git a/test/CodeGen/PowerPC/sdag-ppcf128.ll b/test/CodeGen/PowerPC/sdag-ppcf128.ll
index 535ece6d3d..c46bc6b22d 100644
--- a/test/CodeGen/PowerPC/sdag-ppcf128.ll
+++ b/test/CodeGen/PowerPC/sdag-ppcf128.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mattr=-crbits < %s | FileCheck %s
;
; PR14751: Unsupported type in SelectionDAG::getConstantFP()
diff --git a/test/CodeGen/PowerPC/setcc_no_zext.ll b/test/CodeGen/PowerPC/setcc_no_zext.ll
index 9b2036e1dc..467e921f74 100644
--- a/test/CodeGen/PowerPC/setcc_no_zext.ll
+++ b/test/CodeGen/PowerPC/setcc_no_zext.ll
@@ -1,5 +1,9 @@
; RUN: llc < %s -march=ppc32 | not grep rlwinm
+; FIXME: This optimization has temporarily regressed with crbits enabled by
+; default at the default CodeOpt level.
+; XFAIL: *
+
define i32 @setcc_one_or_zero(i32* %a) {
entry:
%tmp.1 = icmp ne i32* %a, null ; <i1> [#uses=1]
diff --git a/test/CodeGen/PowerPC/seteq-0.ll b/test/CodeGen/PowerPC/seteq-0.ll
index 731958374e..b7dd78085e 100644
--- a/test/CodeGen/PowerPC/seteq-0.ll
+++ b/test/CodeGen/PowerPC/seteq-0.ll
@@ -1,9 +1,12 @@
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
-; RUN: grep "srwi r., r., 5"
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s
define i32 @eq0(i32 %a) {
%tmp.1 = icmp eq i32 %a, 0 ; <i1> [#uses=1]
%tmp.2 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1]
ret i32 %tmp.2
+
+; CHECK: cntlzw [[REG:r[0-9]+]], r3
+; CHECK: rlwinm r3, [[REG]], 27, 31, 31
+; CHECK: blr
}
diff --git a/test/CodeGen/PowerPC/subsumes-pred-regs.ll b/test/CodeGen/PowerPC/subsumes-pred-regs.ll
index 97ac788164..da637cd254 100644
--- a/test/CodeGen/PowerPC/subsumes-pred-regs.ll
+++ b/test/CodeGen/PowerPC/subsumes-pred-regs.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=ppc64 | FileCheck %s
+; RUN: llc < %s -mcpu=ppc64 -mattr=-crbits | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-06 03:08:59 +0000