diff options
Diffstat (limited to 'test/CodeGen')
-rw-r--r-- | test/CodeGen/CellSPU/and_ops.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/CellSPU/call_indirect.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/CellSPU/nand.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/CellSPU/or_ops.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/CellSPU/select_bits.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/CellSPU/struct_1.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/Mips/cprestore.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/Mips/largeimmprinting.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/X86/legalize-libcalls.ll | 35 | ||||
-rw-r--r-- | test/CodeGen/X86/sse3.ll | 24 |
11 files changed, 67 insertions, 29 deletions
diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll index 72478a1ca6..4203e91068 100644 --- a/test/CodeGen/CellSPU/and_ops.ll +++ b/test/CodeGen/CellSPU/and_ops.ll @@ -5,6 +5,9 @@ ; RUN: grep andhi %t1.s | count 30 ; RUN: grep andbi %t1.s | count 4 +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll index 141361d570..1d687d906a 100644 --- a/test/CodeGen/CellSPU/call_indirect.ll +++ b/test/CodeGen/CellSPU/call_indirect.ll @@ -15,6 +15,9 @@ ; RUN: grep ai %t2.s | count 9 ; RUN: grep dispatch_tab %t2.s | count 6 +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + ; ModuleID = 'call_indirect.bc' target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128" target triple = "spu-unknown-elf" diff --git a/test/CodeGen/CellSPU/nand.ll b/test/CodeGen/CellSPU/nand.ll index b770cad8df..57ac709c54 100644 --- a/test/CodeGen/CellSPU/nand.ll +++ b/test/CodeGen/CellSPU/nand.ll @@ -3,6 +3,10 @@ ; RUN: grep and %t1.s | count 94 ; RUN: grep xsbh %t1.s | count 2 ; RUN: grep xshw %t1.s | count 4 + +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/or_ops.ll b/test/CodeGen/CellSPU/or_ops.ll index 4f1febbad7..f329266a3c 100644 --- a/test/CodeGen/CellSPU/or_ops.ll +++ b/test/CodeGen/CellSPU/or_ops.ll @@ -6,6 +6,9 @@ ; RUN: grep orbi %t1.s | count 15 ; RUN: FileCheck %s < %t1.s +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/select_bits.ll b/test/CodeGen/CellSPU/select_bits.ll index c804256f51..65e0aa6fa0 100644 --- a/test/CodeGen/CellSPU/select_bits.ll +++ b/test/CodeGen/CellSPU/select_bits.ll @@ -1,6 +1,9 @@ ; RUN: llc < %s -march=cellspu > %t1.s ; RUN: grep selb %t1.s | count 56 +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll index adbb5efa28..8c3275080c 100644 --- a/test/CodeGen/CellSPU/struct_1.ll +++ b/test/CodeGen/CellSPU/struct_1.ll @@ -22,6 +22,9 @@ ; RUN: grep shufb %t2.s | count 7 ; RUN: grep stqd %t2.s | count 7 +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + ; ModuleID = 'struct_1.bc' target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/Mips/cprestore.ll b/test/CodeGen/Mips/cprestore.ll index 391f5c714d..a275c8b7a5 100644 --- a/test/CodeGen/Mips/cprestore.ll +++ b/test/CodeGen/Mips/cprestore.ll @@ -1,8 +1,4 @@ -; DISABLED: llc -march=mipsel < %s | FileCheck %s -; RUN: false - -; byval is currently unsupported. -; XFAIL: * +; RUN: llc -march=mipsel < %s | FileCheck %s ; CHECK: .set macro ; CHECK-NEXT: .cprestore diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll index 579a319d5f..fcc20f7994 100644 --- a/test/CodeGen/Mips/largeimmprinting.ll +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -1,8 +1,4 @@ -; DISABLED: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s -; RUN: false - -; byval is currently unsupported. -; XFAIL: * +; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s %struct.S1 = type { [65536 x i8] } diff --git a/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll b/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll index 2890c22ce6..ed55bb5dcf 100644 --- a/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll +++ b/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll @@ -1,11 +1,7 @@ -; DISABLED: llc -mtriple=thumbv6-apple-darwin < %s -; RUN: false +; RUN: llc -mtriple=thumbv6-apple-darwin < %s ; rdar://problem/9416774 ; ModuleID = 'reduced.ll' -; byval is currently unsupported. -; XFAIL: * - target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-ios" diff --git a/test/CodeGen/X86/legalize-libcalls.ll b/test/CodeGen/X86/legalize-libcalls.ll new file mode 100644 index 0000000000..879dc98ab2 --- /dev/null +++ b/test/CodeGen/X86/legalize-libcalls.ll @@ -0,0 +1,35 @@ +; RUN: llc -march=x86 < %s +; RUN: llc -march=x86-64 < %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128" + +define float @MakeSphere(float %theta.079) nounwind { +entry: + %add36 = fadd float %theta.079, undef + %call = call float @cosf(float %theta.079) nounwind readnone + %call45 = call float @sinf(float %theta.079) nounwind readnone + %call37 = call float @sinf(float %add36) nounwind readnone + store float %call, float* undef, align 8 + store float %call37, float* undef, align 8 + store float %call45, float* undef, align 8 + ret float %add36 +} + +define hidden fastcc void @unroll_loop(i64 %storemerge32129) nounwind { +entry: + call fastcc void @copy_rtx() nounwind + call fastcc void @copy_rtx() nounwind + %tmp225 = alloca i8, i64 %storemerge32129, align 8 ; [#uses=0 type=i8*] + %cmp651201 = icmp slt i64 %storemerge32129, 0 ; [#uses=1 type=i1] + br i1 %cmp651201, label %for.body653.lr.ph, label %if.end638.for.end659_crit_edge + +for.body653.lr.ph: ; preds = %entry + unreachable + +if.end638.for.end659_crit_edge: ; preds = %entry + unreachable +} + +declare float @cosf(float) nounwind readnone +declare float @sinf(float) nounwind readnone +declare hidden fastcc void @copy_rtx() nounwind diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 8b3a317ffb..d05c45321b 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -16,10 +16,8 @@ entry: ret void ; X64: t0: -; X64: movddup (%rsi), %xmm0 -; X64: pshuflw $0, %xmm0, %xmm0 -; X64: xorl %eax, %eax -; X64: pinsrw $0, %eax, %xmm0 +; X64: movdqa (%rsi), %xmm0 +; X64: pslldq $2, %xmm0 ; X64: movdqa %xmm0, (%rdi) ; X64: ret } @@ -31,9 +29,8 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind { ret <8 x i16> %tmp3 ; X64: t1: -; X64: movl (%rsi), %eax ; X64: movdqa (%rdi), %xmm0 -; X64: pinsrw $0, %eax, %xmm0 +; X64: pinsrw $0, (%rsi), %xmm0 ; X64: ret } @@ -168,7 +165,7 @@ define internal void @t10() nounwind { ret void ; X64: t10: ; X64: pextrw $4, [[X0:%xmm[0-9]+]], %eax -; X64: unpcklpd [[X1:%xmm[0-9]+]] +; X64: movlhps [[X1:%xmm[0-9]+]] ; X64: pshuflw $8, [[X1]], [[X2:%xmm[0-9]+]] ; X64: pinsrw $2, %eax, [[X2]] ; X64: pextrw $6, [[X0]], %eax @@ -250,13 +247,12 @@ entry: %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > ret <16 x i8> %tmp9 ; X64: t16: -; X64: pinsrw $0, %eax, [[X1:%xmm[0-9]+]] -; X64: pextrw $8, [[X0:%xmm[0-9]+]], %eax -; X64: pinsrw $1, %eax, [[X1]] -; X64: pextrw $1, [[X1]], %ecx -; X64: movd [[X1]], %edx -; X64: pinsrw $0, %edx, %xmm -; X64: pinsrw $1, %eax, %xmm +; X64: movdqa %xmm1, %xmm0 +; X64: pslldq $2, %xmm0 +; X64: pextrw $1, %xmm0, %eax +; X64: movd %xmm0, %ecx +; X64: pinsrw $0, %ecx, %xmm0 +; X64: pextrw $8, %xmm1, %ecx ; X64: ret } |