summaryrefslogtreecommitdiff
path: root/include/llvm/CodeGen
Commit message (Expand)AuthorAge
* Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen2012-11-29
* Make the LiveRegMatrix analysis available to targets.Jakob Stoklund Olesen2012-11-28
* misched: Analysis that partitions the DAG into subtrees.Andrew Trick2012-11-28
* misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick2012-11-28
* llvm/CodeGen: Remove empty files in r168659.NAKAMURA Takumi2012-11-27
* Remove unused MachineLoopRanges analysis.Jakub Staszak2012-11-27
* Revert r168635 "Step towards implementation of pass manager with doInitializa...Owen Anderson2012-11-27
* Step towards implementation of pass manager with doInitialization and doFinal...Owen Anderson2012-11-26
* Fix a place where the declaration didn't use LLVM_ENABLE_DUMP but theChandler Carruth2012-11-20
* Fix physical register liveness calculations:Tim Northover2012-11-20
* [reg scavenger] Fix the isUsed/isAliasUsed functions so as to not report a falseChad Rosier2012-11-15
* Use empty parens for empty function parameter list instead of '(void)'.Dmitri Gribenko2012-11-15
* Fix commentAnton Korobeynikov2012-11-14
* Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov2012-11-14
* misched: Don't consider artificial edges weak edges.Andrew Trick2012-11-13
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-12
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-12
* misched: Heuristics based on the machine model.Andrew Trick2012-11-07
* misched: handle on-the-fly regpressure queries better for 2-addrAndrew Trick2012-11-07
* misched: TargetSchedule interface for machine resources.Andrew Trick2012-11-06
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-06
* Add extra declarations of hash_value needed to build llvm with xlc 12.1.Rafael Espindola2012-10-31
* [inline asm] Get the mayLoad/mayStore directly from the MIOp_ExtraInfo operand.Chad Rosier2012-10-30
* [inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier2012-10-30
* In various places throughout the code generator, there were specialUlrich Weigand2012-10-29
* Remove GC roots that reference dead objects.Nicolas Geoffray2012-10-26
* Use ilist rather than std::list for Node and Edge lists in the PBQP graph. ThisLang Hames2012-10-23
* Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerin...Nadav Rotem2012-10-18
* Change MachineFrameInfo::StackObject::Alloca from Value* to AllocaInst*Sebastian Pop2012-10-18
* Temporarily revert the TargetTransform changes.Bob Wilson2012-10-18
* Switch MRI::UsedPhysRegs to a register unit bit vector.Jakob Stoklund Olesen2012-10-17
* Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't useEvan Cheng2012-10-17
* Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().Jakob Stoklund Olesen2012-10-17
* Use a SparseSet instead of a BitVector for UsedInInstr in RAFast.Jakob Stoklund Olesen2012-10-17
* Fix function parameter spelling in comments. Caught by -Wdocumentation.Dmitri Gribenko2012-10-16
* misched: Added handleMove support for updating all kill flags, not just for a...Andrew Trick2012-10-16
* Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen2012-10-15
* Remove LIS::isAllocatable() and isReserved() helpers.Jakob Stoklund Olesen2012-10-15
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-15
* Freeze the reserved registers as soon as isel is complete.Jakob Stoklund Olesen2012-10-15
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-15
* Remove unnecessary classof()'sSean Silva2012-10-11
* Change MachineInstrBuilder::addDisp to copy over target flags by default.Evan Cheng2012-10-11
* Add a new interface to allow IR-level passes to access codegen-specific infor...Nadav Rotem2012-10-10
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-10
* misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick2012-10-09
* misched: Doxument the TargetSchedule API.Andrew Trick2012-10-09
* misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ex...Andrew Trick2012-10-09
* misched: Remove LoopDependencies heuristic.Andrew Trick2012-10-09
* Add in some interfaces that will allow easier access to the pointer address s...Micah Villmow2012-10-09