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path: root/include/llvm/IR/IntrinsicsMips.td
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* [mips][msa] Add DLSA instruction.Matheus Almeida2014-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201081 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS: mark intrinsics IntrNoMem so all patterns using them are consistent.Tim Northover2014-01-21
| | | | | | | | This is apparently a bit of a white lie (they can affect DSPControl for overflow etc) but similar to how we currently handle floating-point operations. When it becomes relevant the whole lot can be reviewed properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199718 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Correct sld and sldi builtins.Daniel Sanders2013-12-10
| | | | | | | | | | | | | | | Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196910 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related testsDaniel Sanders2013-10-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from ↵Daniel Sanders2013-10-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-30
| | | | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-21
| | | | | | | | | The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added lsa instructionDaniel Sanders2013-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192895 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Removed ldx.[bhwd] and stx.[bhwd].Daniel Sanders2013-10-17
| | | | | | | | | | These were present in a previous version of the MSA spec but are not present in the published version. There is no hardware that uses these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192888 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented insert.d intrinsic.Daniel Sanders2013-09-27
| | | | | | | | | This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented fill.d intrinsic.Daniel Sanders2013-09-27
| | | | | | | | | This intrinsic is lowered into an equivalent BUILD_VECTOR which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented copy_[us].d intrinsic.Daniel Sanders2013-09-27
| | | | | | | | | This intrinsic is lowered into equivalent copy_s.w instructions during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. ↵Daniel Sanders2013-09-24
| | | | | | | | | not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191290 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching insert and copy from normal IR (i.e. ↵Daniel Sanders2013-09-23
| | | | | | | | | | | | not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsicsDaniel Sanders2013-09-11
| | | | | | | | | The elements of the operands should be half the width of the elements of the result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190505 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)Daniel Sanders2013-09-10
| | | | | | | | The dotp_[su].b instructions never existed in any revision of the MSA spec. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190398 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added IntrNoMem and removed Commutative from sub intrinsics.Daniel Sanders2013-09-03
| | | | | | | | | | | | | | | | | | | This changes the SelectionDAG nodes from ISD::INTRINSIC_W_CHAIN to ISD::INTRINSIC_WO_CHAIN which enables easy lowering to equivalent SelectionDAG nodes (e.g. __builtin_msa_sub_w -> ISD::SUB) in future patches since nodes such as ISD::SUB do not have a chain. It also corrects an obvious mistake, namely that the subtract intrinsics were marked as being commutative. As per a similar change in r189106 (http://llvm.org/viewvc/llvm-project?rev=189106&view=rev) there isn’t a new testcase in this patch since the existing tests should test the intrinsics to the same standard and the best I can do for a testcase would be a fragile pass/maybe test of whether memory operations can (and do) cross the intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189784 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added IntrNoMem to the floating-point intrinsics.Daniel Sanders2013-09-03
| | | | | | | | | | | | | | | | | This changes the SelectionDAG nodes from ISD::INTRINSIC_W_CHAIN to ISD::INTRINSIC_WO_CHAIN which enables easy lowering to equivalent SelectionDAG nodes (e.g. __builtin_msa_fadd_w -> ISD::FADD) in future patches since nodes such as ISD::FADD do not have a chain. As per a similar change in r189106 (http://llvm.org/viewvc/llvm-project?rev=189106&view=rev) there isn’t a new testcase in this patch since the existing tests should test the intrinsics to the same standard and the best I can do for a testcase would be a fragile pass/maybe test of whether memory operations can (and do) cross the intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189782 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.vDaniel Sanders2013-08-28
| | | | | | | | | | | | | | | These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added load/store intrinsics.Daniel Sanders2013-08-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added move.vDaniel Sanders2013-08-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189471 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added cfcmsa, and ctcmsaDaniel Sanders2013-08-28
| | | | | | | | | The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ↵Daniel Sanders2013-08-28
| | | | | | ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189467 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Few MSA Builtins have side-effects. Added IntrNoMem to those ↵Daniel Sanders2013-08-23
| | | | | | that don't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189106 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Removed fcge, fcgt, fsge, fsgtDaniel Sanders2013-08-20
| | | | | | | | | These instructions were present in a draft spec but were removed before publication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added insveDaniel Sanders2013-08-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188777 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.vDaniel Sanders2013-08-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips][msa] Added the simple builtins (madd_q to xori)Jack Carter2013-08-15
| | | | | | | | | | | | | Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188460 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips][msa] Added the simple builtins (fadd to ftq)Jack Carter2013-08-15
| | | | | | | | | | | | | Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188458 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)Jack Carter2013-08-15
| | | | | | | | | | | | | | Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove "Commutative" from property list of non-commutative intrinsics.Akira Hatanaka2013-05-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180988 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-02
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
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