| Commit message (Expand) | Author | Age |
* | Do not model all INLINEASM instructions as having unmodelled side effects. | Evan Cheng | 2011-01-07 |
* | Move Value::getUnderlyingObject to be a standalone | Dan Gohman | 2010-12-15 |
* | Two sets of changes. Sorry they are intermingled. | Evan Cheng | 2010-11-03 |
* | Putting r117193 back except for the compile time cost. Rather than assuming f... | Evan Cheng | 2010-10-27 |
* | Neuter r117193 as it causes significant post-ra scheduler compile time regres... | Evan Cheng | 2010-10-25 |
* | Properly model the latency of register defs which are 1) function returns or | Evan Cheng | 2010-10-23 |
* | Avoid compiler warning: comparison between signed and unsigned integer. | Evan Cheng | 2010-10-08 |
* | Fix operand latency computation in cases where the definition operand is | Evan Cheng | 2010-10-08 |
* | Remove unused variables. | Nick Lewycky | 2010-10-06 |
* | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng | 2010-10-06 |
* | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng | 2010-09-29 |
* | Teach if-converter to be more careful with predicating instructions that would | Evan Cheng | 2010-09-10 |
* | Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectors | Bob Wilson | 2010-07-24 |
* | Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. | Bill Wendling | 2010-07-15 |
* | Fix the post-RA instruction scheduler to handle instructions referenced by | Jim Grosbach | 2010-05-19 |
* | Get rid of the EdgeMapping map. Instead, just check for BasicBlock | Dan Gohman | 2010-05-01 |
* | Fix -Wcast-qual warnings. | Dan Gohman | 2010-04-17 |
* | Reduce indentation. | Evan Cheng | 2010-03-22 |
* | 80 col violation. | Evan Cheng | 2010-03-22 |
* | Progress towards shepherding debug info through SelectionDAG. | Dale Johannesen | 2010-03-10 |
* | There are two ways of checking for a given type, for example isa<PointerType>(T) | Duncan Sands | 2010-02-16 |
* | Fix dependencies added to model memory aliasing for post-RA scheduling. The d... | David Goodwin | 2009-11-09 |
* | Correctly add chain dependencies around calls and unknown-side-effect instruc... | David Goodwin | 2009-11-05 |
* | <rdar://problem/7352605>. When building schedule graph use mayAlias informati... | David Goodwin | 2009-11-03 |
* | Chain dependencies used to enforce memory order should have latency of 0 (exc... | David Goodwin | 2009-11-02 |
* | When checking whether a def of an aliased register is dead, ask the | Dan Gohman | 2009-10-26 |
* | Spill slots cannot alias. | Evan Cheng | 2009-10-18 |
* | -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed | Evan Cheng | 2009-10-18 |
* | Factor out LiveIntervalAnalysis' code to determine whether an instruction | Dan Gohman | 2009-10-09 |
* | Replace TargetInstrInfo::isInvariantLoad and its target-specific | Dan Gohman | 2009-10-07 |
* | Improve MachineMemOperand handling. | Dan Gohman | 2009-09-25 |
* | Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ... | Evan Cheng | 2009-09-18 |
* | Use the schedule itinerary operand use/def cycle information to adjust depend... | David Goodwin | 2009-08-19 |
* | Add callback to allow target to adjust latency of schedule dependency edge. | David Goodwin | 2009-08-13 |
* | Post RA scheduler changes. Introduce a hazard recognizer that uses the target... | David Goodwin | 2009-08-10 |
* | Fix a typo in a comment. | Dan Gohman | 2009-08-07 |
* | Eliminate yet another copy of getOpcode. | Dan Gohman | 2009-07-17 |
* | Move isLCSSAForm, isLoopInvariant, getCanonicalInductionVariable, | Dan Gohman | 2009-07-13 |
* | When scheduling a block in parts, keep track of the overall | Dan Gohman | 2009-02-11 |
* | Factor out more code for computing register live-range informationfor | Dan Gohman | 2009-02-10 |
* | Move ScheduleDAGInstrs.h to be a private header. Front-ends | Dan Gohman | 2009-02-06 |
* | Fix a post-RA scheduling dependency bug. | Dan Gohman | 2009-01-30 |
* | Instead of adding dependence edges between terminator instructions | Dan Gohman | 2009-01-16 |
* | Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph | Dan Gohman | 2009-01-15 |
* | Clean up the atomic opcodes in SelectionDAG. | Dan Gohman | 2008-12-23 |
* | Rename BuildSchedUnits to BuildSchedGraph, and refactor the | Dan Gohman | 2008-12-23 |
* | Use isTerminator() instead of isBranch()||isReturn() in | Dan Gohman | 2008-12-23 |
* | Add initial support for back-scheduling address computations, | Dan Gohman | 2008-12-16 |
* | Fix some register-alias-related bugs in the post-RA scheduler liveness | Dan Gohman | 2008-12-16 |
* | Add a simple target-independent heuristic to allow targets with no | Dan Gohman | 2008-12-16 |