llvm - Unofficial llvm GIT mirror used in EmbToolkit

	Commit message (Expand)	Author	Age
*	misched prep: Expose the ScheduleDAGInstrs interface so targets may	Andrew Trick	2012-03-07
*	misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs.	Andrew Trick	2012-03-07
*	misched prep: Comment the ScheduleDAGInstrs interface.	Andrew Trick	2012-03-07
*	misched prep: Cleanup ScheduleDAGInstrs interface.	Andrew Trick	2012-03-07
*	misched prep: remove extra "protected"	Andrew Trick	2012-03-07
*	misched prep: rename InsertPos to End.	Andrew Trick	2012-03-07
*	misched preparation: rename core scheduler methods for consistency.	Andrew Trick	2012-03-07
*	comment	Andrew Trick	2012-03-07
*	misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.	Andrew Trick	2012-03-07
*	ScheduleDAGInstrs comments	Andrew Trick	2012-03-07
*	misched preparation: modularize schedule emission.	Andrew Trick	2012-03-07
*	Cleanup in preparation for misched: Move DAG visualization logic.	Andrew Trick	2012-03-07
*	Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ...	Andrew Trick	2012-03-07
*	misched comments	Andrew Trick	2012-03-07
*	ScheduleDAGInstrs.h:155: warning: suggest parentheses around `&&' within `\|\|'.	Nick Lewycky	2012-02-24
*	PostRA sched: speed up physreg tracking by not abusing SparseSet.	Andrew Trick	2012-02-24
*	PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.	Andrew Trick	2012-02-23
*	misched: Use SparseSet for VRegDegs for constant time clear().	Andrew Trick	2012-02-22
*	Initialize SUnits before DAG building.	Andrew Trick	2012-02-22
*	misched: Initial code for building an MI level scheduling DAG	Andrew Trick	2012-01-14
*	Move physreg dependency generation into aptly named addPhysRegDeps.	Andrew Trick	2012-01-14
*	misched: Added ScheduleDAGInstrs::IsPostRA	Andrew Trick	2012-01-14
*	Added a late machine instruction copy propagation pass. This catches	Evan Cheng	2012-01-07
*	PostRA scheduler fix. Clear stale loop dependencies.	Andrew Trick	2011-10-07
*	whitespace	Andrew Trick	2011-10-07
*	Update DBG_VALUEs while breaking anti dependencies.	Devang Patel	2011-06-02
*	During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALU...	Devang Patel	2011-06-02
*	Properly model the latency of register defs which are 1) function returns or	Evan Cheng	2010-10-23
*	Teach if-converter to be more careful with predicating instructions that would	Evan Cheng	2010-09-10
*	Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectors	Bob Wilson	2010-07-24
*	When processing loops for scheduling latencies (used for live outs on loop	Jim Grosbach	2010-06-29
*	I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it	Duncan Sands	2010-05-11
*	Get rid of the EdgeMapping map. Instead, just check for BasicBlock	Dan Gohman	2010-05-01
*	Progress towards shepherding debug info through SelectionDAG.	Dale Johannesen	2010-03-10
*	Spill slots cannot alias.	Evan Cheng	2009-10-18
*	Remove a redundant member variable.	Dan Gohman	2009-10-12
*	Factor out LiveIntervalAnalysis' code to determine whether an instruction	Dan Gohman	2009-10-09
*	Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ...	Evan Cheng	2009-09-18
*	Use the schedule itinerary operand use/def cycle information to adjust depend...	David Goodwin	2009-08-19
*	When scheduling a block in parts, keep track of the overall	Dan Gohman	2009-02-11
*	Factor out more code for computing register live-range informationfor	Dan Gohman	2009-02-10
*	Move ScheduleDAGInstrs.h to be a private header. Front-ends	Dan Gohman	2009-02-06