| Commit message (Expand) | Author | Age |
|---|
| * | Reapply r143206, with fixes. Disallow physical register lifetimes | Dan Gohman | 2011-11-03 |
| * | Revert r143206, as there are still some failing tests. | Dan Gohman | 2011-10-29 |
| * | Reapply r143177 and r143179 (reverting r143188), with scheduler | Dan Gohman | 2011-10-28 |
| * | Speculatively disable Dan's commits 143177 and 143179 to see if | Duncan Sands | 2011-10-28 |
| * | Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW | Dan Gohman | 2011-10-28 |
| * | Change this overloaded use of Sched::Latency to be an overloaded | Dan Gohman | 2011-10-24 |
| * | Remove a now dead function, fixing -Wunused-function warnings from | Chandler Carruth | 2011-10-21 |
| * | Delete the list-tdrr scheduler. Top-down schedulers are going away | Dan Gohman | 2011-10-20 |
| * | PreRA scheduler should avoid cloning compares. | Andrew Trick | 2011-09-01 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 |
| * | More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. | Evan Cheng | 2011-06-27 |
| * | pre-RA-sched: Cleanup register pressure tracking. | Andrew Trick | 2011-06-27 |
| * | Distinguish early clobber output operands from clobbered registers. | Jakob Stoklund Olesen | 2011-06-27 |
| * | Fix some trailing issues from my introduction of MVT::untyped and its use for... | Owen Anderson | 2011-06-21 |
| * | Remove unused but set variables. | Benjamin Kramer | 2011-06-18 |
| * | Add a new MVT::untyped. This will be used in future work for modelling ISA f... | Owen Anderson | 2011-06-15 |
| * | Added -stress-sched flag in the Asserts build. | Andrew Trick | 2011-06-15 |
| * | Remove a temporary test case probe in CheckForLiveRegDef. | Andrew Trick | 2011-06-08 |
| * | Fix a merge bug in preRAsched for handling physreg aliases. | Andrew Trick | 2011-06-07 |
| * | Be careful about scheduling nodes above previous calls. It increase usages of | Evan Cheng | 2011-04-26 |
| * | Fix typo | Evan Cheng | 2011-04-26 |
| * | In the pre-RA scheduler, maintain cmp+br proximity. | Andrew Trick | 2011-04-14 |
| * | Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor lat... | Andrew Trick | 2011-04-13 |
| * | Revert 129383. It causes some targets to hit a scheduler assert. | Andrew Trick | 2011-04-12 |
| * | PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency. | Andrew Trick | 2011-04-12 |
| * | Added a check in the preRA scheduler for potential interference on a | Andrew Trick | 2011-04-07 |
| * | Fix for -pre-RA-sched=source. | Andrew Trick | 2011-03-25 |
| * | Ensure that def-side physreg copies are scheduled above any other uses | Andrew Trick | 2011-03-23 |
| * | whitespace | Andrew Trick | 2011-03-23 |
| * | Grammar-o. | Eric Christopher | 2011-03-21 |
| * | Re-commit 127368 and 127371. They are exonerated. | Evan Cheng | 2011-03-10 |
| * | Revert 127368 and 127371 for now. | Evan Cheng | 2011-03-09 |
| * | Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more | Evan Cheng | 2011-03-09 |
| * | Fix typo, make helper static. | Benjamin Kramer | 2011-03-09 |
| * | Fix some latent bugs if the nodes are unschedulable. We'd gotten away | Eric Christopher | 2011-03-08 |
| * | Further improvements to pre-RA-sched=list-ilp. | Andrew Trick | 2011-03-08 |
| * | Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo. | Cameron Zwarich | 2011-03-07 |
| * | Typo. | Eric Christopher | 2011-03-06 |
| * | Disable a couple of experimental heuristics to get the best results from the ... | Andrew Trick | 2011-03-06 |
| * | Be explicit with abs(). Visual Studio workaround. | Andrew Trick | 2011-03-05 |
| * | Missing comment. | Andrew Trick | 2011-03-05 |
| * | Increased the register pressure limit on x86_64 from 8 to 12 | Andrew Trick | 2011-03-05 |
| * | Minor pre-RA-sched fixes and cleanup. | Andrew Trick | 2011-03-04 |
| * | Introducing a new method of tracking register pressure. We can't | Andrew Trick | 2011-02-04 |
| * | Remove a temporary workaround for a lencod miscompile. Depends on the fix in ... | Andrew Trick | 2011-01-27 |
| * | Temporarily workaround JM/lencod miscompile (SIGSEGV). | Andrew Trick | 2011-01-24 |
| * | Enable support for precise scheduling of the instruction selection | Andrew Trick | 2011-01-21 |
| * | Convert -enable-sched-cycles and -enable-sched-hazard to -disable | Andrew Trick | 2011-01-21 |
| * | Selection DAG scheduler register pressure heuristic fixes. | Andrew Trick | 2011-01-20 |
| * | Support for precise scheduling of the instruction selection DAG, | Andrew Trick | 2011-01-14 |
