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path: root/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Commit message (Expand)AuthorAge
* The "excess register pressure" returned by HighRegPressure() is not accurate ...Evan Cheng2010-07-26
* Pacify gcc-4.5 which wrongly thinks that RExcess (passed as the Excess parame...Duncan Sands2010-07-26
* Add comments.Evan Cheng2010-07-25
* Fix crashes when scheduling a CopyToReg node -- getMachineOpcode asserts onBob Wilson2010-07-25
* Add an ILP scheduler. This is a register pressure aware scheduler that'sEvan Cheng2010-07-24
* - Allow target to specify when is register pressure "too high". In most cases,Evan Cheng2010-07-23
* Re-apply r109079 with fix.Evan Cheng2010-07-22
* Revert r109079, which broke a lot of CodeGen tests.Owen Anderson2010-07-22
* Initialize RegLimit only when register pressure is being tracked.Evan Cheng2010-07-22
* More register pressure aware scheduling work.Evan Cheng2010-07-21
* Teach bottom up pre-ra scheduler to track register pressure. Work in progress.Evan Cheng2010-07-21
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-29
* Use `llvm::next' instead of `next' to make VC++ 2010 happy.Oscar Fuentes2010-05-30
* Fix some latency computation bugs: if the use is not a machine opcode do not ...Evan Cheng2010-05-28
* Eliminate the use of PriorityQueue and just use a std::vector,Dan Gohman2010-05-26
* Delete an unused function.Dan Gohman2010-05-26
* Change push_all to a non-virtual function and implement it in theDan Gohman2010-05-26
* Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.Evan Cheng2010-05-21
* Allow targets more controls on what nodes are scheduled by reg pressure, what...Evan Cheng2010-05-20
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-20
* Three changes:Chris Lattner2010-04-07
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-09
* When the scheduler unfold a load folding instruction it move some of the pred...Evan Cheng2010-02-05
* Remove the '-disable-scheduling' flag and replace it with the 'source' option ofBill Wendling2010-01-23
* The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 ...Bill Wendling2010-01-06
* Only check the ordering if there is an ordering for each nodes.Bill Wendling2010-01-06
* Add a semi-primitive form of scheduling via the "SDNode ordering" to theBill Wendling2010-01-05
* Change errs() to dbgs().David Greene2010-01-05
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-25
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-25
* The ScheduleDAG framework now requires an AliasAnalysis argument, thoughDan Gohman2009-10-09
* Silence comparison always false warning in -Asserts mode.Reid Kleckner2009-09-30
* Fix integer overflow in instruction scheduling. This can happen if we haveReid Kleckner2009-09-30
* eliminate uses of cerr()Chris Lattner2009-08-23
* remove a few DOUTs here and there.Chris Lattner2009-08-23
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ...Owen Anderson2009-08-11
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ...Owen Anderson2009-08-10
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-14
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-11
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-29
* Second attempt:Bill Wendling2009-04-29
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-28
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-28
* In the list-burr's pseudo two-addr dependency heuristics, don'tDan Gohman2009-04-16
* Handle SUBREG_TO_REG instructions with the same heuristicsDan Gohman2009-04-16
* Minor compile-time optimization; don't bother checkingDan Gohman2009-03-24
* Add a pre-pass to the burr-list scheduler which makes adjustments toDan Gohman2009-03-24
* When unfolding a load during scheduling, the new operator node hasDan Gohman2009-03-23
* Fix canClobberPhysRegDefs to check all SDNodes grouped togetherDan Gohman2009-03-23
* For inline asm output operand that matches an input. Encode the input operand...Evan Cheng2009-03-20